Abstract:
A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.
Abstract:
A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.
Abstract:
A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.
Abstract:
A data storage device that includes a novel resistive cross point memory cell array and a method of making the data storage device are described. The resistive cross point memory cell array enables high-density fabrication and high-speed operation with isolation diodes that have practical dimensions and current density characteristics. In addition, the data storage device includes a novel equipotential isolation circuit that substantially avoids parasitic currents that otherwise might interfere with the sensing of the resistance state of the memory cells. In one aspect, the memory cells of the resistive cross point memory cell array are arranged into multiple groups of two or more memory cells. The memory cells of each group are connected between a respective word line and a common isolation diode that is coupled to a bit line.
Abstract:
The invention provides a printed circuit board (PCB) printing system. In a particular embodiment, the system includes a liquid electrophotographic printing device. At least one supplier of electrically conductive ink supplying electrically conductive ink to the electrophotographic printing device is also provided. In addition, at least one supplier of dielectric ink supplying dielectric ink to the electrophotographic printing device is also provided. The liquid electrophotographic printing device is operable to apply the electrically conductive ink and the dielectric ink to a provided substrate such that substantially immiscible boundary delineation occurs at any points of contact between the applied electrically conducive ink and the applied dielectric ink. An appropriate method of use for the rendering of a printed circuit board is also provided.
Abstract:
The invention provides a printed circuit board (PCB) printing system. In a particular embodiment, the system includes a liquid electrophotographic printing device. At least one supplier of electrically conductive ink supplying electrically conductive ink to the electrophotographic printing device is also provided. In addition, at least one supplier of dielectric ink supplying dielectric ink to the electrophotographic printing device is also provided. The liquid electrophotographic printing device is operable to apply the electrically conductive ink and the dielectric ink to a provided substrate such that substantially immiscible boundary delineation occurs at any points of contact between the applied electrically conducive ink and the applied dielectric ink. An appropriate method of use for the rendering of a printed circuit board is also provided.
Abstract:
A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.
Abstract:
An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.
Abstract:
A semiconductor storage device including a tip electrode, a media electrode and a storage media. The storage media has a storage area configurable to be in one of a plurality of structural states to represent information stored at the storage area, by passing a current through the storage area between the tip electrode and media electrode.
Abstract:
A method of performing a thermally assisted write operation on a selected two conductor spin valve memory (SVM) cell having a material wherein the coercivity is decreased upon an increase in temperature. In a particular embodiment, a first write magnetic field is established by a first write current flowing from a first voltage potential to a second voltage potential as applied to the first conductor. A second write magnetic field is established by a second write current flowing from a third voltage potential to a fourth voltage potential as applied to the second conductor. The voltage potential of the first conductor is greater than the voltage potential of the second conductor. As a result, a third current, flows from the first conductor through the SVM cell to the second conductor. The SVM cell has an internal resistance such that the flowing current generates heat within the SVM cell. As the SVM cell is self heated, the coercivity of the SVM cell falls below the combined write magnetic fields.