公开(公告)号：US20080023699A1

公开(公告)日：2008-01-31

申请号：US11460209

申请日：2006-07-26

Applicant: Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L23/58

CPC classification number: H01L22/34 ,  H01L2224/73204 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

Abstract translation: 半导体工艺测试结构包括电极，电荷俘获层和扩散区域。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

公开(公告)号：US20070285976A1

公开(公告)日：2007-12-13

申请号：US11450605

申请日：2006-06-09

Applicant: Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

Inventor： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.

Abstract translation: 存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。 存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。 存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个 状态。 电压脉冲具有基于选择状态的幅度。

公开(公告)号：US20070236237A1

公开(公告)日：2007-10-11

申请号：US11279224

申请日：2006-04-10

Applicant: Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-l Wu

Inventor： Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-l Wu

IPC: G01R31/26

CPC classification number: H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.

Abstract translation: 半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用CV测量来检测是否发生了Vfb偏移。 如果处理步骤导致电荷效应，则感应电荷将不均匀。 如果测试结构的充电不均匀，则不会有Vfb偏移。 然后可以使用延迟反转点技术来监视充电状态。

公开(公告)号：US07262427B2

公开(公告)日：2007-08-28

申请号：US10966335

申请日：2004-10-15

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: H01L29/04

CPC classification number: H01L45/06 ,  H01L27/2472 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/16

Abstract: A phase change device includes a first contact electrode structure a phase change material and a first insulating material between the phase change material and the first contact electrode structure and a second contact electrode in contact with the phase change material. A contact structure formed in the first insulating material between the first contact electrode structure and the phase change material is also included. The contact structure is formed by an insulating material breakdown process. A method of forming a phase change device is also described.

Abstract translation: 相变装置包括第一接触电极结构，相变材料和相变材料与第一接触电极结构之间的第一绝缘材料和与相变材料接触的第二接触电极。 还包括在第一接触电极结构和相变材料之间形成在第一绝缘材料中的接触结构。 接触结构由绝缘材料击穿过程形成。 还描述了形成相变装置的方法。

公开(公告)号：US20070161193A1

公开(公告)日：2007-07-12

申请号：US11327792

申请日：2006-01-06

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract translation: 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

公开(公告)号：US07206227B1

公开(公告)日：2007-04-17

申请号：US11326855

申请日：2006-01-06

Applicant: Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

Inventor： Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/0466 ,  G11C16/0491

Abstract: An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can include a trapping layer. The trapping layer can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the layer. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

Abstract translation: 辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有植入在p型衬底上的n +源极区和n +漏极区。 栅电极可以形成在衬底上以及源区和漏区的部分之上。 栅电极可以包括捕获层。 捕获层可以被电分为两侧。 一侧可以称为“AC侧”，并且可以通过在层内捕获电子而将其固定在高电压。 电子被称为辅助电荷。 另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。

公开(公告)号：US07092038B2

公开(公告)日：2006-08-15

申请号：US10370450

申请日：2003-02-24

Applicant: Yang-Hong Shih ,  Ming-Hsiu Lee

Inventor： Yang-Hong Shih ,  Ming-Hsiu Lee

IPC: H04N9/78

CPC classification number: H04N9/78

Abstract: The present invention provides an adaptive Y/C separation circuit for video signal processing that is capable of correcting previous color discrepancy in separating the luminance (Y) and chrominance (C) signals from the color video signals. In the process, the correlation of video signals on referencing scanning lines is analyzed by transposing the chrominance signals onto a two-dimensional UV plane. A correlation coefficient is obtained through the analysis for adjusting the video signals in the direction of the actual chrominance level, thus separating the luminance and chrominance signals with relatively low cost circuit implementation.

Abstract translation: 本发明提供了一种用于视频信号处理的自适应Y / C分离电路，其能够校正从彩色视频信号中分离亮度（Y）和色度（C）信号的先前颜色差异。 在该过程中，通过将色度信号转换到二维UV平面来分析参考扫描线上的视频信号的相关性。 通过用于在实际色度电平方向上调整视频信号的分析获得相关系数，从而以相对低成本的电路实现分离亮度和色度信号。

公开(公告)号：US20050254296A1

公开(公告)日：2005-11-17

申请号：US10846006

申请日：2004-05-14

Applicant: Hang-Ting Lue ,  Ming-Hsiu Lee

Inventor： Hang-Ting Lue ,  Ming-Hsiu Lee

IPC: G11C5/14 ,  G11C11/36

CPC classification number: G11C5/147

Abstract: A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

Abstract translation: 提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。 该方法包括将第一电压施加到字线解码晶体管的第一栅极。 该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。 该方法还包括将位线解码晶体管的源电压保持在大约零。

公开(公告)号：US06903410B1

公开(公告)日：2005-06-07

申请号：US10710765

申请日：2004-08-02

Applicant: Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: H01L29/792

CPC classification number: H01L29/7923

Abstract: An electrically erasable programmable read only memory cell has a stacking layer, a gate conductive layer, a first source/drain region, a second source/drain region, a first pocket implant doping region, and a second pocket implant doping region. The stacking layer is disposed over a substrate. The gate conductive layer is located on the stacking layer. The first source/drain region and the second source/drain region are respectively disposed over the substrate on two sides of the gate conductive layer. The first pocket implant doping region is disposed over the substrate under the stacking layer, and adjacent to the first source/drain region. The second pocket implant doping region is disposed over the substrate under the stacking layer, and adjacent to the second source/drain region, wherein the doping concentration of the first pocket implant region is different from that of the second pocket implant region.

Abstract translation: 电可擦除可编程只读存储器单元具有堆叠层，栅极导电层，第一源极/漏极区域，第二源极/漏极区域，第一腔体注入掺杂区域和第二凹穴注入掺杂区域。 堆叠层设置在基板上。 栅极导电层位于堆叠层上。 第一源极/漏极区域和第二源极/漏极区域分别设置在栅极导电层的两侧上的衬底上。 第一凹穴注入掺杂区域设置在堆叠层下面的衬底上，并且与第一源极/漏极区域相邻。 第二袋状注入掺杂区域设置在堆叠层下面的衬底上，并且与第二源极/漏极区域相邻，其中第一凹穴注入区域的掺杂浓度不同于第二凹穴注入区域的掺杂浓度。

公开(公告)号：US06890819B2

公开(公告)日：2005-05-10

申请号：US10605253

申请日：2003-09-18

Applicant: Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: H01L21/336 ,  H01L27/10

CPC classification number: H01L27/10

Abstract: A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.

Abstract translation: 描述了形成PN结的方法。 形成由N掺杂（或P掺杂）层，电介质层和成核层组成的堆叠结构，然后形成其中具有开口的绝缘层。 将p掺杂（或N掺杂）多晶硅或非晶硅层填充到开口中，然后退火以转化为单晶硅层。 然后，介电层被分解以形成PN结。