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    Nonvolatile memory device and method for fabricating the same
    21.
    发明申请
    Nonvolatile memory device and method for fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20100133598A1

    公开(公告)日：2010-06-03

    申请号：US12592871

    申请日：2009-12-03

    Applicant: Soodoo Chae ,  Myoungbum Lee

    Inventor： Soodoo Chae ,  Myoungbum Lee

    IPC: H01L29/78

    CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

    Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱和多个栅电极。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极包括第一栅电极和第二栅电极。 第一栅电极设置在存储单元区域上以与有源支柱相交。 第二栅电极设置在接触区域上，连接到第一栅电极并且包括金属材料。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME
    22.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    三维半导体存储器件及其形成方法

    公开(公告)号：US20150333084A1

    公开(公告)日：2015-11-19

    申请号：US14810845

    申请日：2015-07-28

    Applicant: Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    Inventor： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L27/115

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

    Abstract: Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

    Abstract translation: 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150060988A1

    公开(公告)日：2015-03-05

    申请号：US14519821

    申请日：2014-10-21

    Applicant: Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

    Inventor： Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

    IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

    Abstract translation: 半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层 所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

    Semiconductor Memory Device and Method of Fabricating the Same
    25.
    发明申请
    Semiconductor Memory Device and Method of Fabricating the Same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20140220750A1

    公开(公告)日：2014-08-07

    申请号：US14171056

    申请日：2014-02-03

    Applicant: Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    Inventor： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

    Abstract translation: 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

    Three-dimensional nonvolatile memory device
    26.
    发明授权
    Three-dimensional nonvolatile memory device 有权
    三维非易失性存储器件

    公开(公告)号：US08786007B2

    公开(公告)日：2014-07-22

    申请号：US12592871

    申请日：2009-12-03

    Applicant: Soodoo Chae ,  Myoungbum Lee

    Inventor： Soodoo Chae ,  Myoungbum Lee

    IPC: H01L29/792

    CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

    Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱和多个栅电极。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极包括第一栅电极和第二栅电极。 第一栅电极设置在存储单元区域上以与有源支柱相交。 第二栅电极设置在接触区域上，连接到第一栅电极并且包括金属材料。

    Multilayer semiconductor devices with channel patterns having a graded grain structure
    28.
    发明授权
    Multilayer semiconductor devices with channel patterns having a graded grain structure 有权
    具有沟道图案的具有渐变晶粒结构的多层半导体器件

    公开(公告)号：US08507918B2

    公开(公告)日：2013-08-13

    申请号：US13018833

    申请日：2011-02-01

    Applicant: Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

    Inventor： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L29/04

    CPC classification number: H01L27/11582

    Abstract: Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.

    Abstract translation: 存储器件包括布置在衬底上的交错导电图案和绝缘图案的堆叠。 半导体图形通过导体图案和绝缘图案堆叠以接触衬底，半导体图案具有渐变的晶粒尺寸分布，其中半导体图案的靠近衬底的第一部分中的平均晶粒尺寸小于平均晶粒尺寸 在从衬底进一步去除的半导体图案的第二部分中。 分级粒度分布可以通过例如部分激光退火来实现。

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