公开(公告)号：US20160197086A1

公开(公告)日：2016-07-07

申请号：US15070247

申请日：2016-03-15

申请人： JinGyun KIM ,  Myoungbum LEE ,  Seungmok SHIN

发明人： JinGyun KIM ,  Myoungbum LEE ,  Seungmok SHIN

IPC分类号： H01L27/115 ,  H01L23/522

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L23/5226 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.

摘要翻译： 一种制造半导体器件的方法，包括形成电荷存储层，以及形成覆盖电荷存储层的第一隧道绝缘层，形成包括对电荷存储层进行热处理的第一隧道绝缘层。

公开(公告)号：US20130273728A1

公开(公告)日：2013-10-17

申请号：US13912441

申请日：2013-06-07

申请人： JinGyun KIM ,  Myoungbum LEE ,  Seungmok SHIN

发明人： JinGyun KIM ,  Myoungbum LEE ,  Seungmok SHIN

IPC分类号： H01L21/28

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L23/5226 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.

摘要翻译： 一种制造半导体器件的方法，包括形成电荷存储层，以及形成覆盖电荷存储层的第一隧道绝缘层，形成包括对电荷存储层进行热处理的第一隧道绝缘层。

公开(公告)号：US20170133400A1

公开(公告)日：2017-05-11

申请号：US15414345

申请日：2017-01-24

申请人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

发明人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

IPC分类号： H01L27/11582 ,  H01L29/04 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

公开(公告)号：US20150311214A1

公开(公告)日：2015-10-29

申请号：US14790969

申请日：2015-07-02

申请人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

发明人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

IPC分类号： H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

摘要翻译： 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20140070302A1

公开(公告)日：2014-03-13

申请号：US13974122

申请日：2013-08-23

申请人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

发明人： Dongchul YOO ,  Phil Ouk NAM ,  Junkyu YANG ,  Woong LEE ,  Woosung LEE ,  JinGyun KIM ,  Daehong EOM

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

摘要翻译： 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20130134492A1

公开(公告)日：2013-05-30

申请号：US13587379

申请日：2012-08-16

申请人： Junkyu YANG ,  Phil Ouk NAM ,  JinGyun KIM ,  Jaeyoung AHN ,  SeungHyun LIM ,  Kihyun HWANG

发明人： Junkyu YANG ,  Phil Ouk NAM ,  JinGyun KIM ,  Jaeyoung AHN ,  SeungHyun LIM ,  Kihyun HWANG

IPC分类号： H01L29/78

CPC分类号： H01L27/1157 ,  H01L27/11582

摘要： Example embodiments of inventive concepts relate to semiconductor memory devices and/or methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel penetrating the plurality of gates and a data storage layer between the vertical channel and the plurality of gates. The vertical channel may include a lower channel connected to the substrate and an upper channel on the lower channel. The upper channel may include a vertical pattern penetrating some of the plurality of gates and defining an inner space filled with an insulating layer, and a horizontal pattern horizontally extending along a top surface of the lower channel. The horizontal pattern may be in contact with the top surface of the lower channel.

摘要翻译： 本发明构思的示例性实施例涉及半导体存储器件和/或其制造方法。 半导体存储器件可以包括垂直堆叠在衬底上的多个栅极，穿过多个栅极的垂直沟道和垂直沟道与多个栅极之间的数据存储层。 垂直通道可以包括连接到基板的下通道和下通道上的上通道。 上部通道可以包括穿透多个栅极中的一些的垂直图案，并且限定填充有绝缘层的内部空间，以及沿着下部通道的顶表面水平延伸的水平图案。 水平图案可以与下通道的顶表面接触。