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    NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20110101443A1

    公开(公告)日：2011-05-05

    申请号：US12894615

    申请日：2010-09-30

    Applicant: ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

    Inventor： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

    IPC: H01L29/792

    CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

    Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

    Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 层叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE
    4.
    发明申请
    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE 审中-公开
    用于制造非易失性存储器件的方法

    公开(公告)号：US20130005104A1

    公开(公告)日：2013-01-03

    申请号：US13615890

    申请日：2012-09-14

    Applicant: ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

    Inventor： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

    IPC: H01L21/336

    CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

    Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

    Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 堆叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20150249093A1

    公开(公告)日：2015-09-03

    申请号：US14574456

    申请日：2014-12-18

    Applicant: Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

    Inventor： Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

    IPC: H01L27/115

    CPC classification number: H01L27/11582

    Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

    Abstract translation: 提供了一种半导体器件，其包括在衬底上的栅极结构，栅极结构平行于第一方向延伸并且通过插入其间的分离沟槽彼此间隔开，每个栅极结构包括堆叠在衬底上的绝缘图案， 栅电极插入其间; 通过栅极结构连接到衬底的垂直柱; 隔离沟槽中的绝缘间隔物覆盖每个栅极结构的侧壁; 以及在栅电极和绝缘间隔物之间​​的扩散阻挡结构。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150060988A1

    公开(公告)日：2015-03-05

    申请号：US14519821

    申请日：2014-10-21

    Applicant: Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

    Inventor： Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

    IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

    Abstract translation: 半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层 所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20150243675A1

    公开(公告)日：2015-08-27

    申请号：US14599933

    申请日：2015-01-19

    Applicant: Tai-Soo LIM ,  Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Myoungbum LEE ,  Yong-Chae JUNG

    Inventor： Tai-Soo LIM ,  Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Myoungbum LEE ,  Yong-Chae JUNG

    IPC: H01L27/115 ,  H01L29/49

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

    Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

    Abstract translation: 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透彼此交替且重复堆叠的绝缘图案和栅电极的垂直沟道结构。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以延伸以连续地覆盖第二栅极导电层的表面。

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