公开(公告)号：US20150064885A1

公开(公告)日：2015-03-05

申请号：US14309018

申请日：2014-06-19

申请人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

发明人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC分类号： H01L27/115 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

摘要翻译： 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：US09040378B2

公开(公告)日：2015-05-26

申请号：US14309018

申请日：2014-06-19

申请人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

发明人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

摘要翻译： 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：US20120064682A1

公开(公告)日：2012-03-15

申请号：US13230447

申请日：2011-09-12

申请人： Kyung-Tae Jang ,  Myoung Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yuo Lee ,  Dae-Hun Choi

发明人： Kyung-Tae Jang ,  Myoung Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yuo Lee ,  Dae-Hun Choi

IPC分类号： H01L21/8239

CPC分类号： H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

摘要： Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

摘要翻译： 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。

公开(公告)号：US20150126007A1

公开(公告)日：2015-05-07

申请号：US14593221

申请日：2015-01-09

申请人： Kyung-Tae Jang ,  Myoungbum Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yup Lee ,  Dae-Hun Choi

发明人： Kyung-Tae Jang ,  Myoungbum Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yup Lee ,  Dae-Hun Choi

IPC分类号： H01L27/115 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

摘要翻译： 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。