公开(公告)号：US10977645B2

公开(公告)日：2021-04-13

申请号：US16897696

申请日：2020-06-10

Applicant: Miles Paschini ,  Nitin Agarwal

Inventor： Miles Paschini ,  Nitin Agarwal

IPC: G06Q20/36 ,  H04L9/06 ,  G06Q20/40

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

公开(公告)号：US07786909B2

公开(公告)日：2010-08-31

申请号：US12337658

申请日：2008-12-18

Applicant: Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

Inventor： Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

IPC: H03M1/06

CPC classification number: H03M1/129 ,  H03M1/069 ,  H03M1/164

Abstract: With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Abstract translation: 使用高速模数转换器（ADC）时，当输入超过ADC的输入范围时，ADC内部的器件可能会进入饱和区，从而导致错误。 这里，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。 如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。 输入过载条件直接发送到ADC的输出数字模块，根据输入过载信号是否超过上限或下限，提供与上限或下限满量程电平相当的输出数字代码。 因此可以将ADC的输入过载恢复时间最小化。

公开(公告)号：US07663415B2

公开(公告)日：2010-02-16

申请号：US11649747

申请日：2007-01-03

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: H03L7/06

CPC classification number: H03L1/022 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract translation: 锁相环（PLL）架构提供跨工艺和温度的压控振荡器（VCO）增益补偿。 可以使用模拟器来计算用于处理和温度转角的每个组合的VCO的最大和最小输出频率的控制电压。 然后从这些控制电压中选择控制电压的最大值和最小值。 使用计数器，在PLL输入时钟的一些周期中，VCO的周期数以二进制形式计数，并存储在用于极端控制电压的锁存器中。 它们之间的差异与典型工艺和温度角的相应差异用于修改电荷泵以改变递送到环路滤波器的电流。 电荷泵位决定后，VCO的输入控制电压连接到电荷泵输出，开始PLL的正常工作。

公开(公告)号：US07642876B2

公开(公告)日：2010-01-05

申请号：US11261449

申请日：2005-10-28

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03K7/08 ,  H03K9/08

CPC classification number: H03K7/08

Abstract: A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.

Abstract translation: PWM发生器系统使用子周期发生器提供改进的占空比分辨率，用于产生具有要产生的最大PWM周期的一小部分的周期的子周期。 积分子周期估计器耦合到所述子周期发生器，以确定用于PWM波形的导通和截止时间的所述子周期的整数。 附加的子周期估计器确定提供开启和关闭时间所需的附加分数子周期。 耦合到积分子周期估计器和附加子周期估计器的定时器控制用于积分和附加分数子周期的开和关时间的PWM输出切换。

公开(公告)号：US07573414B2

公开(公告)日：2009-08-11

申请号：US11951348

申请日：2007-12-06

Applicant: Abhaya Kumar ,  Visvesvarya Pentakota ,  Nitin Agarwal ,  Jagannathan Venkataraman

Inventor： Abhaya Kumar ,  Visvesvarya Pentakota ,  Nitin Agarwal ,  Jagannathan Venkataraman

IPC: H03M1/12

CPC classification number: G05F1/10

Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.

Abstract translation: 提供恒定参考电压的电压源，与输出端子处的负载变化无关。 输出端的有效阻抗（吸入阻抗）被设计为独立于输出端的信号频率。 在一个实施例中，使构成有效阻抗的两个并联阻抗路径之一的电阻等于另一路径的电阻，并且使两个路径的时间常数相等。 结果，有效阻抗与频率无关，并且尽管负载变化，参考电压的强度也保持恒定，而不会出现振铃，直流下垂等。

公开(公告)号：US20090146857A1

公开(公告)日：2009-06-11

申请号：US11951348

申请日：2007-12-06

Applicant: Abhaya Kumar ,  Visvesvarya Pentakota A ,  Nitin Agarwal ,  Jagannathan Venkataraman

Inventor： Abhaya Kumar ,  Visvesvarya Pentakota A ,  Nitin Agarwal ,  Jagannathan Venkataraman

IPC: H03M1/12 ,  G05F1/10

CPC classification number: G05F1/10

Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.

Abstract translation: 提供恒定参考电压的电压源，与输出端子处的负载变化无关。 输出端的有效阻抗（吸入阻抗）被设计为独立于输出端的信号频率。 在一个实施例中，使构成有效阻抗的两个并联阻抗路径之一的电阻等于另一路径的电阻，并且使两个路径的时间常数相等。 结果，有效阻抗与频率无关，并且尽管负载变化，参考电压的强度也保持恒定，而不会出现振铃，直流下垂等。

公开(公告)号：US20080218151A1

公开(公告)日：2008-09-11

申请号：US11964127

申请日：2007-12-26

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: G01R19/00

CPC classification number: G01R29/023 ,  G01R31/31727

Abstract: A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage. The duty cycle for the second clock signal is then calculated using the first elapsed cycle and the second elapsed cycle.

Abstract translation: 一种用于测量片上占空比的方法和电路。 该电路包括电容器，开关电路，电流源，比较器电路和计数器。 电路接收第一时钟信号和第二时钟信号。 第一个时钟信号占空比为50％，第二个信号具有未知的占空比信号。 开关电路首先接收第一时钟信号，然后接收用于测量占空比的第二时钟信号。 比较器电路将比较器电压与第一时钟信号的参考电压进行比较，以使用计数器测量第一次经过的周期。 比较器电路再次将比较器电压与第二时钟信号的参考电压进行比较，以使用计数器测量第二个经过的周期。 在比较器电压等于参考电压的持续时间内，计数器测量对应于第一时钟信号和第二时钟信号的第一经过周期和第二经过周期。 然后使用第一经过循环和第二经过循环来计算第二时钟信号的占空比。

公开(公告)号：US07327300B1

公开(公告)日：2008-02-05

申请号：US11510259

申请日：2006-08-25

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03M1/82

CPC classification number: H03K7/08 ,  H03M1/661 ,  H03M1/822

Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.

Abstract translation: 系统和方法产生具有可变占空比分辨率的脉宽调制信号。 硬件使用最小的硬件来将PWM占空比分辨率提高到0，从而可以获得最高可能的波形分辨率，包括正弦波。 本发明的实施例使用微控制器，W计数器除法，延迟电路，触发器和逻辑门。

公开(公告)号：US07310058B2

公开(公告)日：2007-12-18

申请号：US11160859

申请日：2005-07-13

Applicant: Anand Hariraj Udupa ,  Vikas Kumar Sinha ,  Nitin Agarwal ,  Visvesvaraya A. Pentakota ,  Sandeep Oswal

Inventor： Anand Hariraj Udupa ,  Vikas Kumar Sinha ,  Nitin Agarwal ,  Visvesvaraya A. Pentakota ,  Sandeep Oswal

IPC: H03M1/38

CPC classification number: H03M1/168

Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Abstract translation: 流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC， 减法器和放大）。 由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

公开(公告)号：US20050116760A1

公开(公告)日：2005-06-02

申请号：US10724517

申请日：2003-11-29

Applicant: Anand Udupa ,  Visvesvaraya Pentakota ,  Shakti Rath ,  Gautam Nandi ,  Vineet Mishra ,  Ravishankar Ayyagari ,  Nitin Agarwal

Inventor： Anand Udupa ,  Visvesvaraya Pentakota ,  Shakti Rath ,  Gautam Nandi ,  Vineet Mishra ,  Ravishankar Ayyagari ,  Nitin Agarwal

IPC: H03F1/26 ,  H03F3/45 ,  H03F3/72 ,  H03L5/00

CPC classification number: H03F1/26 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/4565 ,  H03F3/45937 ,  H03F3/72

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract translation: 低压晶体管用于高压环境。 低电压晶体管可用于处理信号的路径以增加吞吐量性能。 通过使用与高压环境相关联的高压电源，可以获得更高的信噪比。 实施各种技术以确保低电压晶体管不被长时间暴露于高电压而损坏。