公开(公告)号：US6152612A

公开(公告)日：2000-11-28

申请号：US871805

申请日：1997-06-09

Applicant: Stan Liao ,  Steve Tjiang ,  Rajesh Gupta

Inventor： Stan Liao ,  Steve Tjiang ,  Rajesh Gupta

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  Y10S707/99944

Abstract: A system and method for system and circuit level design modeling and simulation using the C++ programming language. Program interfaces in a behavior-less base class are provided to allow a circuit designer to model hardware blocks using user processes in C++. The present invention provides for the manipulation of software user processes that represent the behavior of circuit blocks. C++ is advantageous because it is a familiar language for many designers in the computer industry and therefore requires a smaller learning curve. The novel interface provides an efficient implementation of reactivity (waiting and watching) and concurrency (signals and processes) allowing designers to use C++ to model mixed hardware-software systems with a C++ compiler and a library of the present invention without the need of a complex event-driven run-time kernel, often required in other hardware description languages (HDLs). Hardware descriptions of the present invention are readily mapped in to synthesizable intermediate representations and synthesized into hardware implementations using commercially available tools. The novel program interfaces allow user processes, which communicate with signals, to be timed on defined clock edges of various clock objects. User processes respond to events (reactivity) using next( ), wait( ), wait.sub.-- until( ) and watching( ) functions. The present invention provides an efficient mechanism for context switching with reduces processing overhead by using lambdas (delay-evaluated expression objects). The present invention also provides an efficient implementation of representing a circuit's multi-valued logic signals in C++ and also provides an efficient implementation of instantiation of circuit blocks and elements using C++.

Abstract translation: 一种使用C ++编程语言进行系统和电路级设计建模与仿真的系统和方法。 提供无行为基类中的程序接口，以允许电路设计人员使用C ++中的用户进程建模硬件块。 本发明提供了对代表电路块的行为的软件用户进程的操纵。 C ++是有利的，因为它是计算机行业中许多设计人员熟悉的语言，因此需要较小的学习曲线。 新颖的界面提供了反应性（等待和观看）和并发（信号和过程）的有效实现，允许设计人员使用C ++来利用C ++编译器和本发明的库对混合硬件 - 软件系统进行建模，而无需复杂 事件驱动的运行时内核，通常需要其他硬件描述语言（HDL）。 本发明的硬件描述易于映射到可合成的中间表示，并使用市售工具合成到硬件实现中。 新颖的程序接口允许与信号通信的用户进程在各种时钟对象的定义的时钟边缘上被定时。 用户进程使用next（），wait（），wait-until（）和watching（）函数来响应事件（反应性）。 本发明通过使用lambdas（延迟评估的表达对象）来减少处理开销，提供了一种用于上下文切换的有效机制。 本发明还提供了以C ++表示电路的多值逻辑信号的有效实现，并且还提供使用C ++实现电路块和元件的有效实现。

公开(公告)号：US20090204964A1

公开(公告)日：2009-08-13

申请号：US12287833

申请日：2008-10-14

Applicant: Peter F. Foley ,  Rajesh Gupta ,  Rao Cherukuri ,  Jithendra Bethur ,  Brent Haines

Inventor： Peter F. Foley ,  Rajesh Gupta ,  Rao Cherukuri ,  Jithendra Bethur ,  Brent Haines

IPC: G06F9/455 ,  G06F9/00 ,  G06F21/00 ,  G06F15/16 ,  H04L9/08

CPC classification number: G06F21/554 ,  G06F9/45537 ,  G06F9/45558 ,  G06F21/53 ,  G06F21/57 ,  G06F2009/45587 ,  H04L9/3271 ,  H04L2209/127 ,  H04L2209/42 ,  H04L2209/56 ,  H04L2209/603 ,  H04L2209/76 ,  H04L2209/80

Abstract: A platform architecture shifts the networked computing paradigm from PC+Network to a system using trusted mobile internet end-point (MIEP) devices and cooperative agents hosted on a trusted server. The MIEP device can participate in data flows, arbitrate authentication, and/or participate in implementing security mechanisms, all within the context of assured end-to-end security. The MIEP architecture improves platform-level capabilities by suitably (and even dynamically) partitioning what is done at the MIEP nodes, the network, and the server based infrastructure for delivering services.

Abstract translation: 平台架构将网络计算范式从PC +网络转移到使用受信任的移动互联终端（MIEP）设备和托管在可信服务器上的协作代理的系统。 MIEP设备可以在可靠的端到端安全性的上下文中参与数据流，仲裁认证和/或参与实施安全机制。 MIEP架构通过适当地（甚至动态地）分区在MIEP节点，网络和基于服务器的基础设施上完成的功能来提供平台级功能，以提供服务。

公开(公告)号：US20090170259A1

公开(公告)日：2009-07-02

申请号：US12340140

申请日：2008-12-19

Applicant: Brian Edward Hornung ,  Rajesh Gupta ,  Mike Voisard

Inventor： Brian Edward Hornung ,  Rajesh Gupta ,  Mike Voisard

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

Abstract: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates.

Abstract translation: 一个实施例涉及形成集成电路的方法。 在该方法中，沿着第一轴线以第一方式注入至少一种第一导电类型的掺杂剂物质，以形成至少部分地延伸到一些栅极之下的第一袋状注入区域。 然后以第二种方式注入至少一种第一导电类型的掺杂剂物质，该第二种方式不同于沿相对于第一轴线横向旋转的第二轴线的第一种方式，以形成至少部分地延伸到其它栅极之下的第二袋状物注入区域 。

公开(公告)号：US07337418B2

公开(公告)日：2008-02-26

申请号：US10621253

申请日：2003-07-14

Applicant: Sudhakar Kale ,  Amit Chowdhary ,  Phani Saripella ,  Naresh K. Sehgal ,  Rajesh Gupta

Inventor： Sudhakar Kale ,  Amit Chowdhary ,  Phani Saripella ,  Naresh K. Sehgal ,  Rajesh Gupta

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.

Abstract translation: 在一些实施例中，计算机辅助设计系统包括功能规则提取组件，结构规则提取组件和布局规划组件。 结构规律提取组件提供了一种基于逻辑设计的结构特征提取电路（特别是数据路径电路）的规律性的方法。 结构规则提取部件的一些实施例自动生成用于逻辑设计的一组向量。 矢量是一组在功能和结构上相同的模板实例。 由结构规律提取组件生成的向量由布局规划组件使用。 布局规划组件提供从该组矢量生成电路布局的方法。 在一些实施例中，每个矢量对应于电路布局中的一行。

公开(公告)号：US07316941B1

公开(公告)日：2008-01-08

申请号：US11190242

申请日：2005-07-26

Applicant: Rajesh Gupta

Inventor： Rajesh Gupta

IPC: H01L21/332

CPC classification number: H01L29/7436 ,  H01L27/1027 ,  H01L27/105

Abstract: In one embodiment, a thyristor device may be formed in series relationship with a MOSFET. Alternating regions of opposite conductivity type may be formed in semiconductor material for defining source, body and drain regions for the MOSFET device, and in series relationship to the thyristor. A primary dopant for a commonly-shared cathode/anode-emitter and drain/source region may have a concentration that is at least one order of magnitude greater than that of any background dopant therein. In a particular embodiment, the thyristor device and the MOSFET in series relationship therewith collectively define part of a thyristor-based memory.

Abstract translation: 在一个实施例中，晶闸管器件可以与MOSFET串联形成。 可以在用于限定MOSFET器件的源极，主体和漏极区域的半导体材料中形成相反导电类型的交替区域，并且与晶闸管串联。 用于共用阴极/阳极 - 发射极和漏极/源极区的主要掺杂剂可以具有比其中任何背景掺杂剂的浓度至少一个数量级的浓度。 在特定实施例中，晶闸管器件和与其串联的MOSFET共同地限定了基于晶闸管的存储器的一部分。

公开(公告)号：US20060015645A1

公开(公告)日：2006-01-19

申请号：US11166359

申请日：2005-06-24

Applicant: Matt Ocko ,  George Tuma ,  Manish Kalia ,  Sandeep Kalia ,  John Purrier ,  Rajesh Gupta ,  Deepak Khajuria ,  Saumitra Das

Inventor： Matt Ocko ,  George Tuma ,  Manish Kalia ,  Sandeep Kalia ,  John Purrier ,  Rajesh Gupta ,  Deepak Khajuria ,  Saumitra Das

IPC: G06F15/173

CPC classification number: G06F11/2023 ,  H04L67/14 ,  H04L67/2819 ,  H04L67/2861 ,  H04L67/327 ,  H04L69/40

Abstract: A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availability. To maintain transparency to service users and service applications, service users are located on a first network and production servers are located on a second network. The service appliance assumes the addresses of the service users on the second network and the addresses of the production servers on the first network. Thus, the service appliance obtains all network traffic sent between the production server and service users. While the service application is operating correctly, the service appliance forwards network traffic between the two networks using various network layers.

公开(公告)号：US20050233506A1

公开(公告)日：2005-10-20

申请号：US11159514

申请日：2005-06-22

Applicant: Andrew Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh Gupta ,  Kevin Yang

Inventor： Andrew Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh Gupta ,  Kevin Yang

IPC: G11C11/39 ,  H01L29/74 ,  H01L29/749 ,  H01L21/332

CPC classification number: G11C11/39 ,  H01L27/0817 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract translation: 制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。 激活退火可以激活先前为不同区域植入的掺杂剂。 可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。 然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。 再结晶退火可以使用比先前激活退火的温度低的温度。

公开(公告)号：US06594808B1

公开(公告)日：2003-07-15

申请号：US09435112

申请日：1999-11-05

Applicant: Sudhakar Kale ,  Amit Chowdhary ,  Phani Saripella ,  Naresh K. Sehgal ,  Rajesh Gupta

Inventor： Sudhakar Kale ,  Amit Chowdhary ,  Phani Saripella ,  Naresh K. Sehgal ,  Rajesh Gupta

IPC: G06F1750

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.

Abstract translation: 在一些实施例中，计算机辅助设计系统包括功能规则提取组件，结构规则提取组件和布局规划组件。 功能规则提取组件提供了一种基于逻辑设计的功能特征提取电路（特别是数据路径电路）的规律性的方法。 功能规则提取部件的一些实施例自动生成一组模板以覆盖电路。 模板是电路中至少有两个实例的子电路的表示。 由功能规则提取组件生成的模板由结构规则提取组件使用。 结构规律提取组件提供了一种基于逻辑设计的结构特征提取电路（特别是数据路径电路）的规律性的方法。 结构规则提取部件的一些实施例自动生成用于逻辑设计的一组向量。 矢量是一组在功能和结构上相同的模板实例。 由结构规律提取组件生成的向量由布局规划组件使用。 布局规划组件提供从该组矢量生成电路布局的方法。 在一些实施例中，每个矢量对应于电路布局中的一行。

公开(公告)号：US06380569B1

公开(公告)日：2002-04-30

申请号：US09371741

申请日：1999-08-10

Applicant: Hsueh-Rong Chang ,  Rajesh Gupta

Inventor： Hsueh-Rong Chang ,  Rajesh Gupta

IPC: H01L2980

CPC classification number: H01L29/0623 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/7828

Abstract: A high power unipolar FET switch has an N− drift layer; a layer of metal contacts the drift layer via an ohmic contact to provide a drain connection for the FET. Each switch cell has a pair of trenches recessed into the drift layer and separated by a mesa region. Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material; the conductive material in each trench is connected together to provide a gate connection for the FET. A shallow P region extends from the bottom of each trench into the drift layer and around the trench corners. A layer of metal contacts the mesa region via an ohmic contact to provide a source connection for the FET. The structure preferably operates as a “normally-off” device, with the potentials created by the work function difference between the conductive material and the N− mesa region completely depleting the mesa region. A positive gate voltage undepletes the mesa regions, creates accumulation channels adjacent to the oxide side-walls of the trenches, and modulates the mesa region, thereby turning the switch on and allowing current to flow between drain and source via the mesa region and the accumulation channels. The switch's unipolar structure enables the device to exhibit a fast switching speed with very low switching losses.

Abstract translation: 高功率单极FET开关具有N-漂移层; 一层金属通过欧姆接触接触漂移层，为FET提供漏极连接。 每个开关单元具有凹入漂移层并由台面区域分隔开的一对沟槽。 氧化物层排列在每个沟槽的壁和底部，每个沟槽都填充有导电材料; 每个沟槽中的导电材料连接在一起以提供用于FET的栅极连接。 浅P区域从每个沟槽的底部延伸到漂移层中并且围绕沟槽角部延伸。 金属层通过欧姆接触接触台面区域，以提供FET的源极连接。 该结构优选地作为“常关”装置操作，其中由导电材料和N-台面区域之间的功函数差产生的电位完全耗尽台面区域。 正栅极电压消除台面区域，产生与沟槽的氧化物侧壁相邻的积聚通道，并且调制台面区域，从而使开关接通，并允许电流通过台面区域和积累之间在漏极和源极之间流动 频道 开关的单极结构使器件能够以非常低的开关损耗展现出快速的开关速度。

公开(公告)号：US5533179A

公开(公告)日：1996-07-02

申请号：US347665

申请日：1994-12-01

Applicant: Kayhan Kucukcakar ,  Rajesh Gupta ,  Thomas Tkacik

Inventor： Kayhan Kucukcakar ,  Rajesh Gupta ,  Thomas Tkacik

IPC: G06F9/45 ,  G06F17/50 ,  G06F15/00

CPC classification number: G06F8/425 ,  G06F17/5045 ,  G06F8/48

Abstract: An Hardware Description Language (HDL) description file (12) is updated without requiring complete re-assignment of all tokens associated with the HDL statements. The design information is maintained as attributes assigned to the tokens (14). The tokens map onto a block diagram (16). As part of an update to the HDL text file (34), the tokens are compared to see which ones if any have changed. The text lines are compared from left-to-right and right-to-left searching for changes in the text file and associated changes in token mapping (36, 38). All tokens inclusive between the left-most change and right-most change is considered to be different. New tokens are assigned and mapped into the block diagram for the HDL elements that change (40). The mapping of old tokens are removed from the block diagram (42). The mappings from token that did not change are maintained (44).

Abstract translation: 更新硬件描述语言（HDL）描述文件（12），而不需要完全重新分配与HDL语句相关联的所有令牌。 设计信息作为分配给标记的属性（14）进行维护。 令牌映射到框图（16）。 作为HDL文本文件（34）的更新的一部分，将比较令牌以查看哪些更改。 文本行从左到右和从右到左进行比较，搜索文本文件中的更改和令牌映射中相关联的更改（36,38）。 最左边的变化和最右边的变化之间的所有令牌被认为是不同的。 新的令牌被分配并映射到更改（40）的HDL元素的框图中。 旧的令牌的映射从框图中删除（42）。 维持不变的令牌映射（44）。