公开(公告)号：US06841524B1

公开(公告)日：2005-01-11

申请号：US10682698

申请日：2003-10-09

Applicant: Rajesh Patel ,  Joseph Oreste Carnali ,  Ritu Verma

Inventor： Rajesh Patel ,  Joseph Oreste Carnali ,  Ritu Verma

IPC: C11D3/22 ,  C11D9/26 ,  A61K7/50

CPC classification number: C11D3/221 ,  C11D3/222 ,  C11D9/262

Abstract: The present composition comprises bar having small amounts of surfactant and high amounts of sugars which bar maintains good rates of wear and foams adequately. The sugar has unexpectedly been found to structure bars, even when little or no insoluble fatty acid is used, without degrading bar properties.

Abstract translation: 本发明的组合物包含具有少量表面活性剂和大量糖的棒，其中棒保持良好的磨损率和充分的泡沫。 即使在使用少量或不溶性脂肪酸的情况下，糖也意外地被发现为结构条，而不降低酒吧性质。

公开(公告)号：US06678807B2

公开(公告)日：2004-01-13

申请号：US09740803

申请日：2000-12-21

Applicant: Bryan D. Boatright ,  Rajesh Patel ,  Larry Edward Thatcher

Inventor： Bryan D. Boatright ,  Rajesh Patel ,  Larry Edward Thatcher

IPC: G06F1200

CPC classification number: G06F9/3826 ,  G06F9/3834

Abstract: The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.

Abstract translation: 本发明涉及在具有限制性存储器模型的微处理器系统中使用多存储缓冲器转发。 根据本发明的实施例，系统和方法允许由两个或多个存储操作完全覆盖的加载操作以经由存储缓冲器转发来接收数据，从而保持限制性存储器模型的副作用 提高处理器性能而不违反限制性内存模式。 根据本发明的实施例，一种用于具有限制性存储器模型的系统中的多存储缓冲器转发的方法包括执行多个存储指令，执行加载指令，确定由加载指令寻址的存储器区域与缓存线地址匹配 存储器，确定由多个存储指令存储的数据完全覆盖由加载指令寻址的存储器区域，并且向前发送存储区是OK信号。

公开(公告)号：US06269427B1

公开(公告)日：2001-07-31

申请号：US09271493

申请日：1999-03-18

Applicant: Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

Inventor： Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

IPC: G06F1208

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/0831 ,  G06F12/0859

Abstract: A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

Abstract translation: 一种高速缓冲存储器系统，包括被配置为耦合到CPU的加载/存储单元的高速缓存存储器，耦合到所述高速缓存存储器的缓冲器单元和包括多个条目的操作队列，其中每个有效操作队列入口指向条目 在缓冲单元中。 缓冲单元包括多个数据缓冲器，并且每个数据缓冲器与相应的地址标签相关联。 该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的CPU加载操作而发起数据提取事务并在缓冲器单元中分配条目。 高速缓存系统还被配置为响应于在高速缓冲存储器中错过的随后的CPU加载操作来在操作队列中分配条目，而在数据提取完成之前在缓冲器单元中命中。 优选地，系统被配置为在满足所述数据提取时将获取的数据存储在缓冲器单元条目中，并且还被配置为满足来自缓冲器单元条目的操作队列中的未决加载操作。 在优选实施例中，系统被配置为重新加载。 满足指向缓冲单元条目的所有操作队列条目，然后使缓冲单元条目和操作队列条目无效，从缓冲单元条目缓存存储器。 缓冲单元条目优选地每个都包括指示存储在缓冲单元条目中的数据的哪些部分有效的数据有效位。

公开(公告)号：US5998423A

公开(公告)日：1999-12-07

申请号：US940338

申请日：1997-09-30

Applicant: Victor Manneth ,  Rajesh Patel

Inventor： Victor Manneth ,  Rajesh Patel

IPC: A61K8/00 ,  A61K8/49 ,  A61K8/60 ,  A61K31/00 ,  A61K31/437 ,  A61K31/4745 ,  A61K31/4985 ,  A61K31/519 ,  A61K31/52 ,  A61K31/522 ,  A61K45/00 ,  A61P17/00 ,  A61Q5/10 ,  A61Q17/04 ,  A61Q19/02 ,  A61Q19/04 ,  A61K31/505

CPC classification number: A61Q19/04 ,  A61K31/00 ,  A61K31/437 ,  A61K31/4985 ,  A61K31/519 ,  A61K31/52 ,  A61K31/522 ,  A61K31/706 ,  A61K31/7076 ,  A61K8/606 ,  A61Q19/02 ,  A61Q5/10

Abstract: Compositions and methods for the modulation of melanin production are provided in which the active component is an adenosine receptor antagonist or agonist.

Abstract translation: 提供了调节黑色素生成的组合物和方法，其中活性成分是腺苷受体拮抗剂或激动剂。

公开(公告)号：US20210241395A1

公开(公告)日：2021-08-05

申请号：US17222748

申请日：2021-04-05

Applicant: Rajesh Patel

Inventor： Rajesh Patel

IPC: G06Q50/14 ,  G06Q10/04 ,  G01C21/36 ,  G01C21/34

Abstract: A system and method for finding an optimum travel plan for several subsequent destinations. The system can receive several destinations from the user and determine the optimum travel plan. The different destinations can be provided by capturing an address or location from a webpage or uploading an image of the destination.

公开(公告)号：US10179374B2

公开(公告)日：2019-01-15

申请号：US14765074

申请日：2014-02-04

Applicant: James Bovatsek ,  Rajesh Patel

Inventor： James Bovatsek ,  Rajesh Patel

IPC: C03B33/02 ,  B23K26/00 ,  B23K26/40 ,  B23K103/00

Abstract: The present application is directed to a method and apparatus for processing a transparent or semitransparent material with a laser beam resulting in deterministic separation of a single sheet of the material into two or more pieces.

公开(公告)号：US08289850B2

公开(公告)日：2012-10-16

申请号：US13241738

申请日：2011-09-23

Applicant: Lance Hacking ,  Ramana Rachakonda ,  Belliappa Kuttanna ,  Rajesh Patel

Inventor： Lance Hacking ,  Ramana Rachakonda ,  Belliappa Kuttanna ,  Rajesh Patel

IPC: H04L12/28 ,  H04J1/16 ,  G08C15/00 ,  G06F11/00 ,  G01R31/08

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3243 ,  G06F13/42 ,  G06F15/17306 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler.

Abstract translation: 公开了一种互连带宽调节器。 基于在预定的节气门窗口内是否发生了最大数量的交易，互连带宽调节器关闭互连。 最大交易数量和油门窗口均可调。 使用互连带宽调节器可以调整性能，散热和平均功耗等特性。

公开(公告)号：US08018496B2

公开(公告)日：2011-09-13

申请号：US12505887

申请日：2009-07-20

Applicant: Sanjeev Nath ,  Rajesh Patel

Inventor： Sanjeev Nath ,  Rajesh Patel

IPC: H04N5/232 ,  H04W4/00

CPC classification number: H04N7/185 ,  G06F21/6209 ,  G06F2221/2111 ,  G06F2221/2149 ,  H04N5/23203 ,  H04N5/23206 ,  H04N5/23245

Abstract: The invention described is a method and system for preventing image capture and transmission in a restricted or prohibited zone.

Abstract translation: 描述的本发明是一种用于防止受限制或禁止区域中的图像捕获和传输的方法和系统。

公开(公告)号：US07977289B2

公开(公告)日：2011-07-12

申请号：US12115816

申请日：2008-05-06

Applicant: Rajesh Patel ,  Evan Charles Murphy ,  Rosa Mercedes Paredes

Inventor： Rajesh Patel ,  Evan Charles Murphy ,  Rosa Mercedes Paredes

IPC: A61K7/50

CPC classification number: A61Q19/10 ,  A61K8/06 ,  A61K8/26 ,  A61K8/29 ,  A61K8/31 ,  A61K8/345 ,  A61K8/42 ,  A61K8/8152 ,  A61K2800/33 ,  A61Q17/005

Abstract: The invention relates to substantially surfactant free gel compositions comprising hydrophobic and hydrophilic benefit agents. Unexpectedly, the applicants have found these agents deposit with greater substantivity from such liquid gel compositions relative to surfactant-containing lotion.

Abstract translation: 本发明涉及包含疏水和亲水有益剂的基本上无表面活性剂的凝胶组合物。 出乎意料的是，申请人发现，相对于含表面活性剂的洗剂，这些药物从这种液体凝胶组合物中更加亲和地沉积。

公开(公告)号：US20110163862A1

公开(公告)日：2011-07-07

申请号：US13048070

申请日：2011-03-15

Applicant: Sanjeev NATH ,  Rajesh Patel

Inventor： Sanjeev NATH ,  Rajesh Patel

IPC: B60Q9/00

CPC classification number: G08G1/164

Abstract: The invention is directed to methods and systems for sensing the presence of objects in the intended path of an automobile with a system to warn both the operator of the vehicle and the object of regard.

Abstract translation: 本发明涉及用于感测汽车预期路径中物体的存在的方法和系统，其具有警告车辆的操作者和所关注的对象的系统。