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公开(公告)号：US20150377937A1
公开(公告)日：2015-12-31
申请号：US14769528
申请日：2014-02-18
Applicant: ST-ERICSSON SA
Inventor： Nicolas LAFARGUE , Thomas ALOFS
IPC: G01R21/133
CPC classification number: G01R21/133 , G06F11/3037 , G06F11/3062 , G06F11/3419 , G06F2201/88 , Y02D10/34
Abstract: A power consumption measurement method for operating an electronic component during an interval of time includes: logging power states that the component adopts during the interval, interrogating the log to determine the amount of time that the component spent in each power state during interval, and multiplying the rated power consumption for each state by the amount of time spent in each respective state. The power consumptions for each of the states are summed to determine a total power consumption of the component during the interval. Logging the power states may be achieved by counting command line instructions of different types, thus identify the beginning and end of each power state, during the interval. The method may be used to measure and/or benchmark the actual power consumption of a DDR RAM module. An apparatus for carrying out the method is also disclosed.
Abstract translation: 在时间间隔期间操作电子部件的功耗测量方法包括：记录部件在间隔期间采集的功率状态，询问日志以确定组件在间隔期间在每个功率状态下花费的时间量，并且乘以 每个状态的额定功率消耗在每个状态下花费的时间量。 将每个状态的功耗相加以确定该间隔期间该组件的总功耗。 记录功率状态可以通过计数不同类型的命令行指令来实现，从而在间隔期间识别每个功率状态的开始和结束。 该方法可用于测量和/或基准DDR RAM模块的实际功耗。 还公开了一种用于执行该方法的装置。
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公开(公告)号：US09215753B2
公开(公告)日：2015-12-15
申请号：US14138387
申请日：2013-12-23
Applicant: ST-Ericsson SA
Inventor： Nicolas Josso , Erwan Preteseille , Sylviane Roullier
Abstract: There is described a multiple subscriber identity arrangement having a modem capable of receiving messages related to either one of at least two subscriber identities, but not simultaneously. The arrangement further comprises a control unit configured to, when the modem performs communication activity associated with a first subscriber identity: determine whether gaps not allocated for the communication activity associated with the first subscriber identity coincide with paging occasions associated with a second subscriber identity; and, if at least one gap not allocated for the communication activity associated with the first subscriber identity coincides with at least one paging occasion associated with the second subscriber identity, cause the modem to switch to the second subscriber identity to read one paging message on a paging channel associated with the second subscriber identity.
Abstract translation: 描述了具有调制解调器的多用户识别装置，该调制解调器能够接收与至少两个订户身份中的任一个相关的消息，但不能同时接收消息。 该装置还包括一个控制单元，配置成当调制解调器执行与第一用户身份相关联的通信活动时：确定未分配给与第一用户身份相关联的通信活动的间隙是否与与第二用户身份相关联的寻呼时机一致; 并且如果未分配用于与第一用户身份相关联的通信活动的至少一个间隙与与第二用户身份相关联的至少一个寻呼时机一致，则使得调制解调器切换到第二用户身份以读取一个寻呼消息 与第二用户标识相关联的寻呼信道。
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23.发明申请公开(公告)号：US20150349716A1
公开(公告)日：2015-12-03
申请号：US14654861
申请日：2014-01-21
Applicant: ST-ERICSSON SA
Inventor： Pierangelo CONFALONIERI , Federico GUANZIROLI , Germano NICOLLINI
CPC classification number: H03F1/0205 , H03F1/307 , H03F1/3205 , H03F3/183 , H03F3/211 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2178 , H03F3/3059 , H03F3/3064 , H03F3/45179 , H03F2200/03 , H03F2200/351 , H03F2203/21142
Abstract: Differential output stage (200) of an amplification device, for driving a load, comprises a first (201) and a second (202) differential output stage portion. The first differential output stage portion (201) comprises: a first (M1PSW) and a second (M1NSW) output circuit; a first driving circuit (210) comprising a first biasing circuit (M2P, M3N, M4N, R11, I11); a second driving circuit (220) comprising a second biasing circuit (I41, R41, M4P, M3P, M2N). The first differential output stage portion (201) comprises: a third output circuit (M2PSW) connected between a first node (N1) of said first biasing circuit (M2P, M3N, M4N, R11, I11) and a first differential output terminal (01), having a third driving terminal (DT3) connected to a first driving terminal (DT1); a fourth output circuit (M2NSW) connected between a first node (N4) of the second biasing circuit (I41, R41, M4P, M3P, M2N) and the first differential output terminal (01), having a fourth driving terminal (DT4) connected to a second driving terminal (DT2).
Abstract translation: 用于驱动负载的放大装置的差分输出级（200）包括第一（201）和第二（202）差分输出级部分。 第一差分输出级部分（201）包括：第一（M1PSW）和第二（M1NSW）输出电路; 第一驱动电路（210），包括第一偏置电路（M2P，M3N，M4N，R11，I11）; 包括第二偏置电路（I41，R41，M4P，M3P，M2N）的第二驱动电路（220）。 第一差分输出级部分（201）包括：连接在所述第一偏置电路（M2P，M3N，M4N，R11，I11）的第一节点（N1）和第一差分输出端子（01）之间的第三输出电路（M2PSW） ），具有连接到第一驱动端子（DT1）的第三驱动端子（DT3）; 连接在第二偏置电路（I41，R41，M4P，M3P，M2N）的第一节点（N4）和第一差分输出端子（01）之间的第四输出电路（M2NSW），具有连接的第四驱动端子（DT4） 到第二驱动终端（DT2）。
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公开(公告)号：US09204215B2
公开(公告)日：2015-12-01
申请号：US14136484
申请日：2013-12-20
Applicant: ST-Ericsson SA
Inventor： Christian Fraisse , Angelo Nagari
CPC classification number: H04R3/00 , H03F3/2175 , H03F3/45968 , H03F2200/331 , H03F2200/375 , H03M3/384 , H03M3/50
Abstract: There is described Audio driver circuit comprising a main, 1-bit digital-to-analog converter, adapted to receive a 1-bit oversampled digital audio signal. Thanks to an auxiliary digital-to-analog converter which converts into the analog domain a digital offset compensation value stored in e.g. an OTP memory register 34, and to a summing and filtering arrangement, it is possible to reduce the offset cancellation granularity in order to compensate for the offset of the main digital-to-analog converter in the output signal.
Abstract translation: 描述了音频驱动器电路，其包括适用于接收1位过采样数字音频信号的主1位数模转换器。 由于辅助数模转换器，其转换成模拟域，数字偏移补偿值存储在例如数据位。 OTP存储器寄存器34，并且对于求和和滤波装置，可以减小偏移消除粒度，以便补偿主数模转换器在输出信号中的偏移。
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公开(公告)号：US09203415B2
公开(公告)日：2015-12-01
申请号：US14369118
申请日：2013-01-22
Applicant: ST-Ericsson SA
Inventor： David Jacquet , Philip O'Shea , Jacques Prunier
CPC classification number: H03L7/00 , G06F1/12 , H03K5/135 , H04L7/0037
Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).
Abstract translation: 信号同步电路技术领域本发明涉及一种信号同步电路，包括至少一个同步器（2.1-2.2），其包括N个串联连接的时钟延迟元件（3.1-3.3），N等于或大于1，以及时钟信号发生器 ），用于产生适于对所述时钟延迟元件（3.1-3.3）或所述至少一个同步器（2.1-2.2）的元件进行时钟的调制时钟信号。 时钟发生器（1）被布置成接收时钟信号（5）和至少一个操作值（6），并且从根据操作值（5）修改的时钟信号（5）产生调制时钟信号（1 out） 6）。
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Patent Agency Ranking
公开(公告)号：US09202132B2
公开(公告)日：2015-12-01
申请号：US14375174
申请日：2013-02-13
Applicant: ST-Ericsson SA
Inventor： Frederique Roffet
CPC classification number: G06K9/46 , G06K9/342 , G06K9/56 , G06K9/6201 , G06K2009/4666 , G06K2009/6213 , G06T3/40 , G06T5/001 , G06T5/002 , G06T5/20 , G06T5/30 , G06T2207/20021
Abstract: There is described a method for the creation of at least a second, virtual image (200) from a first image (100) captured by a user or retrieved from a storage device to aid interpretation of image content. This allows, for instance, implementing a multishot image quality enhancement scheme based on the real image and the virtual image.
Abstract translation: 描述了从用户捕获的或从存储设备检索的第一图像（100）创建至少第二虚拟图像（200）的方法，以帮助解释图像内容。 这允许例如实现基于真实图像和虚像的多重拍摄图像质量增强方案。
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27.发明授权公开(公告)号：US09191042B2
公开(公告)日：2015-11-17
申请号：US14030305
申请日：2013-09-18
Applicant: ST-Ericsson SA
Inventor： Achraf Dhayni
CPC classification number: H04B1/10 , H04L25/0202 , H04L25/0204 , H04L25/0226 , H04L27/2647 , H04L27/2649 , H04L27/2691
Abstract: An interference cancellation technique is implemented in a receiver adapted for determining an estimation of interferences when receiving an OFDM signal made of packets. Each packet includes a first training field, a second training field, a first header field, a second header field and a data field. The receiver detects a first symbol value of the first header field, and a second symbol value of the second header field, the first and the second header fields having been modulated using different modulation schemes. The estimation of interferences is determined using the first and the second symbol values.
Abstract translation: 在接收适合于在接收由分组构成的OFDM信号时确定干扰估计的接收机中实现干扰消除技术。 每个分组包括第一训练场，第二训练场，第一报头字段，第二报头字段和数据字段。 接收机检测第一报头字段的第一符号值和第二报头字段的第二符号值，第一和第二报头字段已经使用不同的调制方案进行了调制。 使用第一和第二符号值确定干扰的估计。
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公开(公告)号：US20150303994A1
公开(公告)日：2015-10-22
申请号：US14443680
申请日：2013-11-21
Applicant: ST-ERICSSON SA
Inventor： Achraf DHAYNI
CPC classification number: H04B5/0031 , H04B5/0081 , H04W4/80
Abstract: A method of conditioning a first signal transmitted between a first and a second near field communication, NFC, device, the method comprising: determining a transfer function representative of a distortion arising from transfer of a signal from the first NFC device to the second NFC device; determining a pre-distortion function from the transfer function; and applying the pre-distortion function to the first signal, wherein the pre-distortion function at least partially compensates for the determined transfer function.
Abstract translation: 一种调节在第一和第二近场通信NFC装置之间传输的第一信号的方法，所述方法包括：确定代表从第一NFC设备传送到第二NFC设备的信号所产生的失真的传递函数 ; 从传递函数确定预失真函数; 以及将所述预失真函数应用于所述第一信号，其中所述预失真函数至少部分地补偿所确定的传递函数。
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公开(公告)号：US09160231B2
公开(公告)日：2015-10-13
申请号：US14353991
申请日：2012-09-25
Applicant: ST-Ericsson SA
Inventor： Benoit Labbe , David Chesneau
Abstract: A circuit with current-controlled frequency implements a node (2) with an electrical charge which alternatively increases and decreases between two thresholds. The slew rate of the node can be adjusted using a tunable current source (1), thereby enabling tuning of a switching delay. The circuit may be used for controlling the switching frequency of a switch-mode power supply.
Abstract translation: 具有电流控制频率的电路实现具有在两个阈值之间可选地增加和减少的电荷的节点（2）。 可以使用可调电流源（1）来调整节点的转换速率，从而实现对开关延迟的调节。 该电路可用于控制开关模式电源的开关频率。
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30.发明申请Method and Apparatus for Controlling a Start-Up Sequence of a DC/DC Buck Converter 有权控制DC / DC降压转换器启动顺序的方法和装置公开(公告)号：US20150249382A1
公开(公告)日：2015-09-03
申请号：US14426761
申请日：2013-08-15
Applicant: ST-ERICSSON SA
Inventor： Philippe Pignolo
Abstract: A method of controlling a start-up sequence of a DC/DC Buck converter, the method being characterised by the steps of continuously comparing the Buck converter's output voltage with an internal reference voltage and continuously monitoring for a Buck converter start-up signal, wherein if the output voltage is greater than the reference voltage when a Buck converter start-up signal is detected, switching off the Buck converter and discharging an output capacitor of the Buck converter through a pull-down unit until the output voltage substantially equals the internal reference voltage and then restarting the Buck converter.
Abstract translation: 一种控制DC / DC降压转换器的启动顺序的方法，该方法的特征在于以下步骤：将降压转换器的输出电压与内部参考电压进行连续比较，并连续监测降压转换器启动信号，其中 如果当检测到降压转换器启动信号时输出电压大于参考电压，则关闭降压转换器并通过下拉单元对降压转换器的输出电容放电直到输出电压基本上等于内部参考 电压然后重新启动降压转换器。
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