公开(公告)号：US20040141344A1

公开(公告)日：2004-07-22

申请号：US10747969

申请日：2003-12-29

Applicant: STMicroelectronics S.A.

Inventor： Benoit Peron ,  Frederic Gautier

IPC: H02M007/00

CPC classification number: H02M5/257 ,  H02M2001/0006

Abstract: An isolated circuit of low-voltage supply of a control circuit of a high-voltage load, in or upstream of a fullwave three-phase rectifying bridge, comprising a first low-voltage capacitor having a first electrode connected to one of the rectified output terminals of the bridge, and at least one second capacitor providing said low voltage, a first electrode of the second capacitor being connected to one of the A.C. input terminals of the bridge, the respective second electrodes of the capacitors being connected by a high-voltage diode having its cathode connected to the second capacitor.

Abstract translation: 一种在全波三相整流桥或其上游的高电压负载控制电路的低电压供电的隔离电路，包括：第一低电压电容器，其具有连接到整流输出端之一的第一电极 以及提供所述低电压的至少一个第二电容器，所述第二电容器的第一电极连接到所述桥接器的一个AC输入端子，所述电容器的各个第二电极由高压二极管 其阴极连接到第二电容器。

公开(公告)号：US20040136295A1

公开(公告)日：2004-07-15

申请号：US10726421

申请日：2003-12-03

Applicant: STMicroelectronics S.A.

Inventor： Philippe Graffouliere

IPC: G11B007/00

CPC classification number: G11B27/24 ,  G11B7/0053 ,  G11B7/00745 ,  G11B20/14 ,  G11B20/18 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  G11B2220/2562

Abstract: During manufacturing of optical disks, mastering equipment inserts marks (nullhigh frequency wobble marksnull ornullHFWMsnull) into the wobble of the groove on optical disks to store data. The presence of a HFWM at a zero crossing of the wobble indicates an active bit and the absence of the HFWM indicates an inactive bit. The zero crossing is, for example, a negative zero crossing. A matched filter is used to detect the shape of the HFWMs. If a HFWM is detected during a wobble cycle, an active bit is saved in a register or a memory. If a HFWM is not detected during a wobble cycle, an inactive bit is saved in a register or a memory. The active and inactive bits may be coded bits that must be decoded to data bits. The data bits include information such as a synchronization mark, a sector identification data, and an error detection code.

Abstract translation: 在光盘制造过程中，母盘设备将标记（“高频摇摆标记”或“HFWM”）插入到光盘上凹槽的摆动中以存储数据。 HFWM在摆幅过零点处的存在表示有效位，并且HFWM的不存在表示无效位。 过零点例如是负零交叉。 匹配滤波器用于检测HFWM的形状。 如果在摆动周期期间检测到HFWM，则活动位将保存在寄存器或存储器中。 如果在摆动周期期间未检测到HFWM，则无效位将保存在寄存器或存储器中。 有源和无效位可以是必须被解码为数据位的编码位。 数据位包括诸如同步标记，扇区识别数据和错误检测码之类的信息。

公开(公告)号：US20040124930A1

公开(公告)日：2004-07-01

申请号：US10672920

申请日：2003-09-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Thierry Divel ,  Julien Mira

IPC: H03L007/00

CPC classification number: H03B5/1206 ,  H03B5/1243

Abstract: The invention relates to a voltage controlled oscillator comprising a resonator having an inductive circuit and a capacitive circuit whose oscillations are maintained by an active circuit, the capacitive circuit using varactors whose capacitance is adjusted by a control voltage acting in a differential mode with a biasing voltage. According to the invention, the capacitive circuit comprises several capacitive branches connected in parallel, controlled by a same control voltage, but biased by biasing voltages that are different from one branch to the next. The oscillator of the invention features in particular an oscillation frequency, which is much easier to control, and a considerably reduced phase noise.

Abstract translation: 本发明涉及一种压控振荡器，其包括具有感应电路的谐振器和其振荡由有源电路维持的电容电路，所述电容电路使用可变电抗器，其电容通过以偏置电压作用在差分模式的控制电压来调节 。 根据本发明，电容电路包括并联连接的几个电容分支，由相同的控制电压控制，但是通过不同于一个分支到下一个分支的偏置电压来偏置。 本发明的振荡器特别地具有更容易控制的振荡频率和显着降低的相位噪声。

公开(公告)号：US20040122535A1

公开(公告)日：2004-06-24

申请号：US10683567

申请日：2003-10-10

Applicant: STMICROELECTRONICS S.A.

Inventor： Maurice G. Le Van Suu

IPC: G05B013/02

CPC classification number: G05B17/02

Abstract: A control procedure is provided for use during a regulation stage and according to a set point of a physical dynamic system, the set point being subject to, whilst operating, the influence of several physical quantities represented by input parameters, and adopting a behavior defined by at least a first physical output parameter, obliged to take a value represented by the set point, the first output parameter being linked to at least a first of the input parameters by a first transfer function of the system. According to the control procedure, a characterization stage is implemented in which at least a first inverse transfer function linking the first input parameter to the first output parameter is experimentally determined. A modeling stage is implemented in which the first inverse transfer function is translated through a fuzzy logic model in the form of a first set of ranges of the first output parameter, to each of which is attributed a specific value of the first input parameter. The regulation stage is implemented by determining a membership of the set point to one of the ranges of the first set, deducing from the membership and from the fuzzy logic model an estimated value of the first input parameter corresponding to the desired equality between the first output parameter and the set point, producing a measured value of the first input parameter, and regulating the first input parameter according to a difference between the estimated value and the measured value of the first input parameter. The present invention is particularly suited for use with electric motors.

Abstract translation: 提供控制程序，用于在调节阶段期间使用，并且根据物理动态系统的设定点，设定点在运行时受到由输入参数表示的若干物理量的影响，并采用由 至少第一物理输出参数，必须获取由所述设定点表示的值，所述第一输出参数通过所述系统的第一传递函数链接到至少第一输入参数。 根据控制过程，实现表征阶段，其中至少将第一输入参数与第一输出参数相连接的第一反向传递函数实验确定。 实现建模阶段，其中通过模糊逻辑模型以第一输出参数的第一组范围的形式翻译第一反向传递函数，其中每一个归因于第一输入参数的特定值。 调节阶段通过将设定点的成员资格确定为第一组的范围中的一个，从成员资格和从模糊逻辑模型推导出的第一输入参数的估计值对应于第一输出 参数和设定点，产生第一输入参数的测量值，并根据第一输入参数的估计值和测量值之间的差来调节第一输入参数。 本发明特别适用于电动马达。

公开(公告)号：US20040119891A1

公开(公告)日：2004-06-24

申请号：US10678967

申请日：2003-10-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Christophe Barnichon

IPC: H04N005/46

CPC classification number: H04N7/0122 ,  H04N21/4884 ,  Y10S348/913

Abstract: A system and method are provided for displaying a video composed of images each comprising a predetermined number M of lines and, a predetermined number N of pixels in each line. Values of a predetermined number P of reference pixels for each line of a current image of the video are stored in memory, where P is less than N. For each line of the current image, the value of a parameter associated with the line is determined, with the parameter corresponding to the number of the reference pixels of the line that are black according to a first predetermined criterion. A first nonblack line and a last nonblack line of the current image are determined to serve as a basis for an automatic reframing of the images of the video before display. The first nonblack line of the current image is determined by excluding, starting from a first line of the image, the lines of the image which are black according to a second predetermined criterion based on the parameter, and the last nonblack line of the current image is determined by excluding, starting from a last line of the image, the lines of the image which are black according to the second predetermined criterion based on the parameter.

Abstract translation: 提供了一种系统和方法，用于显示由图像组成的视频，每个图像包括预定数量的行和每行中的预定数量的N个像素。 视频的当前图像的每一行的预定数量P个参考像素的值被存储在存储器中，其中P小于N.对于当前图像的每一行，确定与该行相关联的参数的值 具有与根据第一预定标准为黑色的线的参考像素的数量相对应的参数。 确定当前图像的第一非黑色线和最后一条非黑色线作为显示之前的视频图像的自动重构的基础。 当前图像的第一非黑色线通过从图像的第一行开始，基于参数根据第二预定标准排除黑色的图像的行，并且将当前图像的最后一条黑线除去 通过从图像的最后一行开始，基于参数从根据第二预定标准排除黑色的图像的行来确定。

公开(公告)号：US20040066239A1

公开(公告)日：2004-04-08

申请号：US10612335

申请日：2003-07-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Adalberto Mariani ,  Giulio Corva

IPC: H03L007/00

CPC classification number: H02M3/156 ,  G01R23/09 ,  H03K9/06

Abstract: A frequency/signal converter is provided that receives an input clock signal and generates an output signal. The converter includes a first circuit that receives the input clock signal and generates first and second logic signals that are complementary with one another, a loop circuit that includes a first circuit line and a second circuit line that are each coupled between a first supply voltage and a second supply voltage, and an integrator device. A current proportional to the output signal of the converter flows in the loop circuit. The first and second circuit lines include first and second capacitive elements and first and second switches for interrupting current flow into the first and second capacitive elements, respectively. The first and second switches are controlled by the first and second logic signals, respectively. The first and second circuit lines are alternatively coupled to an input terminal of the integrator device in order to obtain a substantially constant voltage signal at the input terminal of the integrator device, and the integrator device provides the output signal of the converter. Also provided is a switching regulator for providing a regulated voltage to a load.

Abstract translation: 提供了一种接收输入时钟信号并产生输出信号的频率/信号转换器。 转换器包括第一电路，其接收输入时钟信号并产生彼此互补的第一和第二逻辑信号;环路电路，包括第一电路线和第二电路线，每个耦合在第一电源电压和 第二电源电压和积分器装置。 与转换器的输出信号成比例的电流在回路中流动。 第一和第二电路线包括第一和第二电容元件以及分别用于中断流入第一和第二电容元件的电流的第一和第二开关。 第一和第二开关分别由第一和第二逻辑信号控制。 第一和第二电路线交替地耦合到积分器装置的输入端，以便在积分器装置的输入端获得基本恒定的电压信号，积分器装置提供转换器的输出信号。 还提供了一种用于向负载提供调节电压的开关调节器。

公开(公告)号：US20040058493A1

公开(公告)日：2004-03-25

申请号：US10621262

申请日：2003-07-15

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics S.A.

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US20040017702A1

公开(公告)日：2004-01-29

申请号：US10453466

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Richard Fournel ,  Jean-Pierre Schoellkopf ,  Philippe Candelier

IPC: G11C029/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract translation: 提供了几次可编程（FTP）存储元件。 FTP存储元件包括一组N个基本存储器单元和多个选择电路。 每个基本存储器单元包括用于连接到主地址总线的地址总线和用于连接到主数据总线的数据总线。 选择电路产生连续的选择信号，用于连续选择一个基本存储器单元，以给予对所选择的一个基本存储单元的独占访问。 选择电路工作，以便在检测到预定条件时自动选择下一个基本存储器单元。 在优选实施例中，每个基本存储器单元是可编程的。

公开(公告)号：US20030227329A1

公开(公告)日：2003-12-11

申请号：US10325589

申请日：2002-12-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Jean-Charles Grasset ,  Frederic Bossu

IPC: H03G003/10

CPC classification number: H03F1/302 ,  H03F2200/372

Abstract: A biasing device includes closed-loop transconductance slaving circuit, able to slave the time average of the base/emitter or gate/source voltage of the amplifier transistor (Q1) to a reference voltage corresponding to a desired quiescent current for the transistor. Moreover, viewed from the base or gate of the amplifier transistor (Q1), the impedance of the base/emitter or gate/source circuit is small at low frequency, and large with respect to the impedance of the radio frequency source within the radio frequency range of the signal. The device can be incorporated in a mobile terminal, such as a cellular mobile phone.

Abstract translation: 偏置装置包括闭环跨导从动电路，其能够将放大器晶体管（Q1）的基极/发射极或栅极/源极电压的时间平均值与对应于晶体管的期望静态电流的参考电压相关联。 此外，从放大晶体管（Q1）的基极或栅极观察，基极/发射极或栅极/源极电路的阻抗在低频时较小，相对于射频内的射频源的阻抗较大 信号范围。 该装置可以结合在诸如蜂窝移动电话的移动终端中。

公开(公告)号：US20030193956A1

公开(公告)日：2003-10-16

申请号：US10417629

申请日：2003-04-16

Applicant: STMicroelectronics S.A.

Inventor： Matthias Dietrich

IPC: H04L012/28

CPC classification number: H04L45/00 ,  H04L45/54 ,  H04L45/7457 ,  H04L69/22

Abstract: A method for routing an information packet towards an output port of a telecommunication router comprising N output ports, said router receiving incoming packets comprising a destination address defined by four address elements. The method successively comprises: looking up a first-level table from said first address element of said information packet; looking up a second-level table from said first and second address elements of said packet; searching, with linear or dichotomizing search, a third-level table allowing a third level of search, from said third address element of said packet; searching, with linear or dichotomizing search, a fourth-level table from said fourth address element of said packet. In this way the size of the routing table can be reduced, while still allowing fast processing of incoming packets. The invention also provides a router allowing easy integration in a VLSI circuit.

Abstract translation: 一种用于将信息包路由到包括N个输出端口的电信路由器的输出端口的方法，所述路由器接收包括由四个地址元素定义的目的地地址的传入分组。 所述方法依次包括：从所述信息包的所述第一地址元素查找第一级表; 从所述分组的所述第一和第二地址元素查找第二级表; 利用线性或二分法搜索，从所述分组的所述第三地址元素搜索允许第三级搜索的第三级表; 利用线性或二分法搜索搜索来自所述分组的所述第四地址元素的第四级表。 以这种方式，可以减少路由表的大小，同时仍然允许快速处理传入的分组。 本发明还提供了一种容易集成在VLSI电路中的路由器。