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公开(公告)号：US12164000B2
公开(公告)日：2024-12-10
申请号：US17460657
申请日：2021-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Cannone , Enrico Ferrara , Nicola Errico , Gea Donzelli
IPC: G01R31/3167 , G01R31/28 , G01R31/317
Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.
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公开(公告)号：US20240395680A1
公开(公告)日：2024-11-28
申请号：US18797031
申请日：2024-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo CREMA
IPC: H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.
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公开(公告)号：US12156303B2
公开(公告)日：2024-11-26
申请号：US17888214
申请日：2022-08-15
Applicant: STMicroelectronics S.r.l.
Inventor： Claudio Adragna , Giovanni Gritti
IPC: H05B45/10 , H02M1/42 , H05B45/385
Abstract: A control circuit includes: a flip-flop having an output configured to be coupled to a control terminal of a transistor and for producing a first signal; a comparator having an output coupled to an input of the flip-flop, and first and second inputs for receiving first and second voltages, respectively; a transconductance amplifier having an input for receiving a sense voltage indicative of a current flowing through the transistor, and an output coupled to the first input of the comparator; a zero crossing detection (ZCD) circuit having an input configured to be coupled to a first current path terminal of the transistor and to an inductor, where the ZCD circuit is configured to detect a demagnetization time of the inductor and produce a third signal based on the detected demagnetization time; and a reference generator configured to generate the second voltage based on the first and third signals.
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公开(公告)号：US12148473B2
公开(公告)日：2024-11-19
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
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公开(公告)号：US12144077B2
公开(公告)日：2024-11-12
申请号：US17490034
申请日：2021-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Giovanni Gritti , Claudio Adragna
IPC: H05B45/325 , H05B45/10 , H05B45/397
Abstract: An LED lighting system includes switching circuitry adjustably driving a string of LEDs and being controlled by a reference current and an enable signal. A controller generates the reference current and enable signal based upon a PWM signal such that the switching circuitry: sources a first LED current to the string of LEDs that is proportional to a duty cycle of the PWM signal when the duty cycle is greater than a threshold duty cycle to thereby perform analog dimming; and sources a second LED current to the string of LEDs that has a duty cycle proportional to the duty cycle of the PWM signal when the duty cycle of the PWM signal is less than the threshold duty cycle, such that an average LED current delivered to the string of LEDs is proportional to the duty cycle of the PWM signal to thereby perform digital dimming.
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Patent Agency Ranking
公开(公告)号：US12143764B2
公开(公告)日：2024-11-12
申请号：US17686322
申请日：2022-03-03
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Federico Rizzardini , Lorenzo Bracco , Andrea Labombarda , Mauro Bardone , Stefano Paolo Rivolta , Federico Iaccarino
Abstract: The present disclosure is directed to input detection for electronic devices using electrostatic charge sensors. The devices and methods disclosed herein utilize electrostatic charge sensors to detect various touch gestures, such as long and short touches, single/double/triple taps, and swipes; and perform in-ear detection.
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公开(公告)号：US12142552B2
公开(公告)日：2024-11-12
申请号：US18070051
申请日：2022-11-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L21/56
Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
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公开(公告)号：US20240371738A1
公开(公告)日：2024-11-07
申请号：US18774478
申请日：2024-07-16
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto TIZIANI
IPC: H01L23/498 , H01L23/00 , H01L23/15 , H01L23/31 , H01L23/488 , H01L23/495 , H01L23/522 , H01L23/538
Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
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公开(公告)号：US12135668B2
公开(公告)日：2024-11-05
申请号：US18056012
申请日：2022-11-16
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Castellano , Francesco Bruni , Luca Gandolfi , Marco Leo
Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.
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公开(公告)号：US12135572B2
公开(公告)日：2024-11-05
申请号：US17694182
申请日：2022-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto Cattani , Alessandro Gasparini , Stefano Ramorini
IPC: G05F1/56
Abstract: In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
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