公开(公告)号：US09229044B2

公开(公告)日：2016-01-05

申请号：US13463166

申请日：2012-05-03

Applicant: Herschel A. Ainspan ,  Seongwon Kim ,  Franco Stellari ,  Alan J. Weger

Inventor： Herschel A. Ainspan ,  Seongwon Kim ,  Franco Stellari ,  Alan J. Weger

IPC: H03K19/00 ,  G01R31/26 ,  H03K19/094 ,  H03K19/14

CPC classification number: H04N17/002 ,  G01J1/44 ,  G01J11/00 ,  G01J2001/4238 ,  G01R31/26 ,  H03K19/094 ,  H03K19/14

Abstract: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

Abstract translation: 示出了PICA测试方法，其包括形成具有近端发光区域的半导体器件，使得发光区域被分组成由目标分辨率尺寸所控制的距离分开的不同形状; 形成逻辑电路以控制半导体器件; 通过提供输入信号来激活所述一个或多个半导体器件; 并且通过向逻辑电路提供一个或多个选择信号来抑制来自一个或多个激活的半导体器件的光发射。

公开(公告)号：US20130280828A1

公开(公告)日：2013-10-24

申请号：US13463166

申请日：2012-05-03

Applicant: HERSCHEL A. AINSPAN ,  Seongwon Kim ,  Franco Stellari ,  Alan J. Weger

Inventor： HERSCHEL A. AINSPAN ,  Seongwon Kim ,  Franco Stellari ,  Alan J. Weger

IPC: H01L21/66

CPC classification number: H04N17/002 ,  G01J1/44 ,  G01J11/00 ,  G01J2001/4238 ,  G01R31/26 ,  H03K19/094 ,  H03K19/14

Abstract: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

Abstract translation: 示出了PICA测试方法，其包括形成具有近端发光区域的半导体器件，使得发光区域被分组成由目标分辨率尺寸所控制的距离分开的不同形状; 形成逻辑电路以控制半导体器件; 通过提供输入信号来激活所述一个或多个半导体器件; 并且通过向逻辑电路提供一个或多个选择信号来抑制来自一个或多个激活的半导体器件的光发射。

公开(公告)号：US08331164B2

公开(公告)日：2012-12-11

申请号：US12960651

申请日：2010-12-06

Applicant: Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

Inventor： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC: G11C7/06

CPC classification number: G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

Abstract: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

Abstract translation: 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

公开(公告)号：US20120140554A1

公开(公告)日：2012-06-07

申请号：US12960651

申请日：2010-12-06

Applicant: Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

Inventor： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC: G11C11/00 ,  G11C7/00 ,  G11C7/06

CPC classification number: G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

Abstract: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

Abstract translation: 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

公开(公告)号：US20120119717A1

公开(公告)日：2012-05-17

申请号：US12944392

申请日：2010-11-11

Applicant: Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jocobson ,  Seongwon Kim

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jocobson ,  Seongwon Kim

IPC: G05F1/10

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.

Abstract translation: 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。

公开(公告)号：US20110019321A1

公开(公告)日：2011-01-27

申请号：US12508665

申请日：2009-07-24

Applicant: Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

Inventor： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

IPC: G01R27/26 ,  H02H3/00

CPC classification number: G01R31/024 ,  G01R31/028

Abstract: A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

Abstract translation: 一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。 每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。 泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。 如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。 可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

公开(公告)号：US07757142B2

公开(公告)日：2010-07-13

申请号：US12174327

申请日：2008-07-16

Applicant: Mohit Kapur ,  Seongwon Kim

Inventor： Mohit Kapur ,  Seongwon Kim

IPC: G01R31/28 ,  G06F11/00

CPC classification number: H04L1/242

Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

Abstract translation: 提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。 被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。 在本发明的一个方面，PRBS检查技术包括以下步骤/操作。 对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。 错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。 然后，错误位的传播在后续的时钟周期被禁止。 禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

公开(公告)号：US20080276139A1

公开(公告)日：2008-11-06

申请号：US12174327

申请日：2008-07-16

Applicant: Mohit Kapur ,  Seongwon Kim

Inventor： Mohit Kapur ,  Seongwon Kim

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: H04L1/242

Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

Abstract translation: 提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。 被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。 在本发明的一个方面，PRBS检查技术包括以下步骤/操作。 对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。 错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。 然后，错误位的传播在后续的时钟周期被禁止。 禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

公开(公告)号：US07279949B2

公开(公告)日：2007-10-09

申请号：US11215416

申请日：2005-08-30

Applicant: Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

Inventor： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

IPC: H03H11/26

CPC classification number: H03H11/265 ,  H03K5/133 ,  H03K2005/00039

Abstract: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Abstract translation: 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

公开(公告)号：US20060181324A1

公开(公告)日：2006-08-17

申请号：US11215416

申请日：2005-08-30

Applicant: Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

Inventor： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

IPC: H03H11/26

CPC classification number: H03H11/265 ,  H03K5/133 ,  H03K2005/00039

Abstract: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Abstract translation: 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。