公开(公告)号：US6064090A

公开(公告)日：2000-05-16

申请号：US671542

申请日：1996-06-27

申请人： Shoichi Miyamoto ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Takashi Ipposhi

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636

摘要： On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions are included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.

摘要翻译： 在绝缘膜上形成台面隔离硅层，其中包括沟道区和源极/漏极区。 栅极绝缘膜和作为栅电极的一部分的导电层堆叠在台面隔离硅层上。 在台面隔离硅层的沟道区的端部的台面隔离硅层，栅极绝缘膜和导电层的侧面形成绝缘材料的侧壁，在 导电层。

公开(公告)号：US08852413B2

公开(公告)日：2014-10-07

申请号：US13637833

申请日：2011-03-30

申请人： Naohide Nishiwaki ,  Shoichi Miyamoto ,  Akitsugu Inagawa ,  Hironobu Murase

发明人： Naohide Nishiwaki ,  Shoichi Miyamoto ,  Akitsugu Inagawa ,  Hironobu Murase

IPC分类号： G01N27/327 ,  C12Q1/00

CPC分类号： G01N27/3272 ,  C12Q1/005

摘要： A biosensor, comprising an insulating base plate, an electrode system containing at least a working electrode and a counter electrode and formed on the insulating base plate, and a sample-supplying section formed on the electrode system, wherein the sample-supplying section has a reaction layer comprising: a first reaction layer formed on the electrode system and containing at least a redox enzyme into which pyrroloquinoline quinone (PQQ), flavin adenine dinucleotide (FAD), or flavin mononucleotide (FMN) is incorporated as a prosthetic group; and a second reaction layer formed by applying, onto the first reaction layer, a solution including a lipid decomposing enzyme.

摘要翻译： 一种生物传感器，包括绝缘基板，至少包含工作电极和对电极并形成在所述绝缘基板上的电极系统以及形成在所述电极系统上的样品供应部分，其中所述样品供应部分具有 反应层包括：形成在电极系统上并含有至少一种氧化还原酶的第一反应层，其中加入吡咯并喹啉醌（PQQ），黄素腺嘌呤二核苷酸（FAD）或黄素单核苷酸（FMN）作为假体基团; 以及通过在第一反应层上施加包含脂质分解酶的溶液而形成的第二反应层。

公开(公告)号：US20100296596A1

公开(公告)日：2010-11-25

申请号：US12851786

申请日：2010-08-06

申请人： Shoichi MIYAMOTO

发明人： Shoichi MIYAMOTO

IPC分类号： H04L27/28 ,  H04L27/00

CPC分类号： H04L5/0041 ,  H04L5/0007 ,  H04L5/0094 ,  H04W72/0453

摘要： A wireless communication technology which realizes high-speed transmission while making effective use of existing frequency bands. A wireless communication apparatus includes a communication unit to perform a wireless communication with a target communication device by simultaneously using a plurality of carrier frequency bands each of which has a specified bandwidth and is discontinuous between each carrier frequency-band interval.

摘要翻译： 一种在有效利用现有频带的同时实现高速传输的无线通信技术。 无线通信装置包括：通信单元，其通过同时使用具有指定带宽的多个载波频带，并且在每个载波频带间隔之间不连续地与目标通信设备进行无线通信。

公开(公告)号：US07515558B2

公开(公告)日：2009-04-07

申请号：US10315712

申请日：2002-12-10

申请人： Shoichi Miyamoto ,  Toshio Kato

发明人： Shoichi Miyamoto ,  Toshio Kato

IPC分类号： H04B7/216

CPC分类号： H04W52/34

摘要： Power control of a base station of a CDMA system that includes a plurality of communication terminals and a maintenance terminal is optimized by adjusting one of transmitted power and received power of the base station, based on power distribution values of radio channels used in radio communications, the power distribution values being obtained by counting the number of the radio channels corresponding to each of the transmitted power levels and the received power levels of the base station.

摘要翻译： 基于在无线电通信中使用的无线电信道的功率分配值，通过调整基站的发射功率和接收功率之一来优化包括多个通信终端和维护终端的CDMA系统的基站的功率控制， 功率分配值通过对与发送的功率电平和基站的接收功率电平相对应的无线电信道的数量进行计数而获得。

公开(公告)号：US07327987B2

公开(公告)日：2008-02-05

申请号：US09814241

申请日：2001-03-21

申请人： Shoichi Miyamoto ,  Masato Tsuji ,  Toshio Kato ,  Masatoshi Watanabe

发明人： Shoichi Miyamoto ,  Masato Tsuji ,  Toshio Kato ,  Masatoshi Watanabe

IPC分类号： H04B7/00

CPC分类号： H04W36/18

摘要： This invention relates to base station control equipment, radio base station equipment and radio terminal equipment that together constitute a mobile communication system. These base station control equipment, radio base station equipment and radio terminal equipment of this invention update transmitting power of a radio channel allotted to a new visit-zone to a greater and suitable value in time sequence. Therefore, mobile communication system according to the invention can keep speech quality of a completed call and transmission quality at high levels, can improve the number of radio channels that can be formed in parallel in a common frequency band (system capacity) or an information content of information that can be transmitted in parallel with desired transmission quality, and can improve utilization efficiency of a radio frequency.

摘要翻译： 本发明涉及一起构成移动通信系统的基站控制设备，无线基站设备和无线终端设备。 本发明的这些基站控制设备，无线基站设备和无线终端设备将分配给新的访问区域的无线电信道的发射功率更新为更合适的时间顺序。 因此，根据本发明的移动通信系统可以将完成的呼叫和传输质量的语音质量保持在高水平，可以改善可以在公共频带（系统容量）或信息内容中并行形成的无线电信道的数量 可以以期望的传输质量并行传输的信息，并且可以提高射频的利用效率。

公开(公告)号：US07024219B2

公开(公告)日：2006-04-04

申请号：US11030399

申请日：2005-01-06

申请人： Shoichi Miyamoto

发明人： Shoichi Miyamoto

IPC分类号： H04Q7/20

CPC分类号： H04W52/265 ,  H04W52/267

摘要： In a mobile communication system 100 of the third generation CDMA type. A base station control apparatus 1 controls a transmission power of an opponent communication apparatus by means of measuring a FER within a predetermined segment, averaging plural pieces of quality information per frame, producing a translation table 40c by means of associating the FER acquired by the measurement and average frame quality information acquired by the averaging, estimating an estimated FER corresponding to the quality information per frame from the translation table 40c, and controlling a target receive power threshold based on the estimated FER and a target FER stored in advance, thereby quickly carrying out the transmission power control, improving the data quality of a lower layer, maintaining the data quality as constant, and increasing the throughput.

摘要翻译： 在第三代CDMA类型的移动通信系统100中。 基站控制装置1通过测量预定段内的FER来控制对方通信装置的发送功率，每帧平均多条质量信息，通过将由 通过平均获取的测量和平均帧质量信息，从转换表40c估计与每帧的质量信息相对应的估计FER，并且基于预先存储的估计FER和目标FER来控制目标接收功率阈值，从而 快速实施传输功率控制，提高下层数据质量，保持数据质量不变，提高吞吐量。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06461935B2

公开(公告)日：2002-10-08

申请号：US09989152

申请日：2001-11-21

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

摘要翻译： 具有与半导体元件区域相邻的沟槽形隔离器的半导体器件形成为具有在向下方向上连续减小的宽度，以缓解硅层中的应力。 实施例包括在SOI衬底上形成图案化的电介质层，在其上形成侧壁间隔物，并蚀刻下面的硅层，接着进行氧化或受控蚀刻，以形成具有向下减少的侧表面的沟槽。

公开(公告)号：US06372599B1

公开(公告)日：2002-04-16

申请号：US09371027

申请日：1999-08-10

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device having the trench-shaped isolator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region, for relaxing the stress in the silicon layer and being flat the surface of the trench-shaped insulator, and method of manufacturing the same.

公开(公告)号：US6127874A

公开(公告)日：2000-10-03

申请号：US939443

申请日：1997-09-29

申请人： Shigemichi Wakabayashi ,  Toshiyuki Oshima ,  Osamu Fuji ,  Shoichi Miyamoto

发明人： Shigemichi Wakabayashi ,  Toshiyuki Oshima ,  Osamu Fuji ,  Shoichi Miyamoto

IPC分类号： H01L21/822 ,  G06F1/10 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H03K19/096 ,  H03K19/173 ,  H03K3/013

CPC分类号： G06F1/10 ,  G06F17/5045

摘要： The present invention provides a semiconductor IC and a method for designing the same which adjusts the clock skews on a chip without additional delay circuit. A decrease in design time is realized when the semiconductor IC includes hard megacells (whose functions have been confirmed) or standard cell blocks. In the case of a semiconductor IC including hard megacells and a standard cell blocks, each megacell and standard cell block according to the present invention has sub-clock buffers on every row, for example, sub-clock buffers on the row and sub-clock buffers on the row in the megacell. The adjustment needed for accommodating clock skews on a chip is determined by calculating a delay time for the various IC chip blocks. Next, sub-clock buffers are chosen based on a result of a calculation for the delay time. Finally, the wiring design is completed which minimizes clock skew.

摘要翻译： 本发明提供一种半导体IC及其设计方法，用于调整芯片上的时钟偏差而不需要额外的延迟电路。 当半导体IC包括硬兆字节（其功能已被确认）或标准单元块时，实现了设计时间的减少。 在包括硬兆赫和标准单元块的半导体IC的情况下，根据本发明的每个兆位和标准单元块在每行上具有子时钟缓冲器，例如行和子时钟上的子时钟缓冲器 在megacell行上的缓冲区。 通过计算各种IC芯片块的延迟时间来确定在芯片上适应时钟偏移所需的调整。 接下来，基于延迟时间的计算结果来选择子时钟缓冲器。 最后，完成了布线设计，使时钟偏移最小化。