公开(公告)号：US07728566B2

公开(公告)日：2010-06-01

申请号：US12127531

申请日：2008-05-27

Applicant: Takaaki Negoro ,  Koichi Morino

Inventor： Takaaki Negoro ,  Koichi Morino

IPC: G05F1/00 ,  G05F1/569 ,  G05F1/571

CPC classification number: G05F1/56

Abstract: A voltage regulator having a MOS transistor driver includes a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage input terminal Vin. A threshold voltage or a voltage lower than the threshold voltage is applied to a gate of the input side p-channel MOS transistor. A drain of the output side p-channel MOS transistor is connected to the voltage output terminal Vout. A current flowing through the input side p-channel MOS transistor drives a voltage regulator circuit and the output side p-channel MOS transistor.

Abstract translation: 具有MOS晶体管驱动器的电压调节器包括电压输入端Vin处的p沟道MOS晶体管和电压输出端Vout的p沟道MOS晶体管。 输入侧p沟道MOS晶体管的漏极连接到电压输入端子Vin。 将阈值电压或低于阈值电压的电压施加到输入侧p沟道MOS晶体管的栅极。 输出侧p沟道MOS晶体管的漏极连接到电压输出端子Vout。 流过输入侧p沟道MOS晶体管的电流驱动电压调节器电路和输出侧p沟道MOS晶体管。

公开(公告)号：US20080218147A1

公开(公告)日：2008-09-11

申请号：US12127531

申请日：2008-05-27

Applicant: Takaaki Negoro ,  Koichi Morino

Inventor： Takaaki Negoro ,  Koichi Morino

IPC: G05F1/10

CPC classification number: G05F1/56

Abstract: A voltage regulator having a MOS transistor driver is disclosed. The voltage regulator comprises a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage input terminal Vin. A threshold voltage or a voltage lower than the threshold voltage is applied to a gate of the input side p-channel MOS transistor. A drain of the output side p-channel MOS transistor is connected to the voltage output terminal Vout.A current flowing through the input side p-channel MOS transistor drives a voltage regulator circuit and the output side p-channel MOS transistor.

Abstract translation: 公开了一种具有MOS晶体管驱动器的稳压器。 电压调节器包括电压输入端Vin处的p沟道MOS晶体管和电压输出端Vout的p沟道MOS晶体管。 输入侧p沟道MOS晶体管的漏极连接到电压输入端子Vin。 将阈值电压或低于阈值电压的电压施加到输入侧p沟道MOS晶体管的栅极。 输出侧p沟道MOS晶体管的漏极连接到电压输出端子Vout。 流过输入侧p沟道MOS晶体管的电流驱动电压调节器电路和输出侧p沟道MOS晶体管。

公开(公告)号：US06894350B2

公开(公告)日：2005-05-17

申请号：US10897089

申请日：2004-07-23

Applicant: Akira Shimizu ,  Takaaki Negoro

Inventor： Akira Shimizu ,  Takaaki Negoro

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same substrate. The gate electrodes and the gate oxide layers of the LDMOS and the MOS are formed independently from one another. The source and drain regions of the LDMOS and the MOS are respectively formed in a self-aligned manner. In this way, the LDMOS and the MOS can be formed, in an effective manner, while sustaining the respective desired characteristics.

Abstract translation: 公开了半导体器件，半导体器件的制造方法和包括半导体器件的集成电路。 半导体器件包括同时在同一衬底上形成的LDMOS晶体管和MOS晶体管。 LDMOS和MOS的栅电极和栅氧化层彼此独立地形成。 LDMOS和MOS的源极和漏极区分别以自对准的方式形成。 以这种方式，可以以有效的方式在保持各自期望的特性的同时形成LDMOS和MOS。

公开(公告)号：US20050017297A1

公开(公告)日：2005-01-27

申请号：US10897089

申请日：2004-07-23

Applicant: Akira Shimizu ,  Takaaki Negoro

Inventor： Akira Shimizu ,  Takaaki Negoro

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/94 ,  H01L29/76

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same substrate. The gate electrodes and the gate oxide layers of the LDMOS and the MOS are formed independently from one another. The source and drain regions of the LDMOS and the MOS are respectively formed in a self-aligned manner. In this way, the LDMOS and the MOS can be formed, in an effective manner, while sustaining the respective desired characteristics.

公开(公告)号：US09749566B2

公开(公告)日：2017-08-29

申请号：US14641683

申请日：2015-03-09

Applicant: Kazuhiro Yoneda ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Yasukazu Nakatani ,  Katsuyuki Sakurano

Inventor： Kazuhiro Yoneda ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Yasukazu Nakatani ,  Katsuyuki Sakurano

IPC: H04N5/374 ,  H04N5/355

CPC classification number: H04N5/374 ,  H04N5/35527

Abstract: An imaging device includes a photoelectric conversion element which photoelectrically converts incident light and generates a charge, accumulates and amplifies the charge, and outputs a photocurrent, wherein a level of an output signal when a charge which is accumulated in the photoelectric conversion element is outputted over a saturated amount of accumulable charge includes a level of an output signal of a charge of a photocurrent of DC component which is generated in the photoelectric conversion element and outputted during a readout time when the charge which is accumulated in the photoelectric conversion element is outputted.

公开(公告)号：US09478568B2

公开(公告)日：2016-10-25

申请号：US14305821

申请日：2014-06-16

Applicant: Katsuhiko Aisu ,  Takaaki Negoro ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano ,  Hirofumi Watanabe

Inventor： Katsuhiko Aisu ,  Takaaki Negoro ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano ,  Hirofumi Watanabe

IPC: H01L27/144 ,  H01L27/146 ,  H04N5/359 ,  H04N5/374 ,  H04N5/3745

CPC classification number: H01L27/144 ,  H01L27/14609 ,  H04N5/359 ,  H04N5/374 ,  H04N5/3745

Abstract: A photoelectric conversion device includes a first output line, a second output line; and a photoelectric conversion cell. The photoelectric conversion cell further includes, a photoelectric conversion element configured to generate an output current corresponding to an intensity of incident light, a first switch element configured to transmit the first output current to the first output line according to a first control signal, and a second switch element configured to transmit the second output current to second output line according to a second control signal. As a result, the photoelectric conversion device can be provided to generate rapidly the image data with wide dynamic range without the need for complex control outside of the photoelectric conversion device.

Abstract translation: 光电转换装置包括第一输出线，第二输出线， 和光电转换单元。 光电转换单元还包括：光电转换元件，被配置为产生与入射光强度相对应的输出电流;第一开关元件，被配置为根据第一控制信号将第一输出电流传输到第一输出线;以及 第二开关元件，被配置为根据第二控制信号将第二输出电流传输到第二输出线。 结果，可以提供光电转换装置以快速生成具有宽动态范围的图像数据，而不需要光电转换装置外部的复杂控制。

公开(公告)号：US20160195431A1

公开(公告)日：2016-07-07

申请号：US14978172

申请日：2015-12-22

Applicant: Katsuhiko Aisu ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Yoshinori Ueda ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

Inventor： Katsuhiko Aisu ,  Hirofumi Watanabe ,  Takaaki Negoro ,  Yoshinori Ueda ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

IPC: G01J1/44

CPC classification number: G01J1/44 ,  G01J2001/444 ,  G01J2001/4473 ,  H04N5/361 ,  H04N5/3655 ,  H04N5/378

Abstract: A photoelectric conversion device includes a pixel cell including a phototransistor, a reference cell including a reference transistor having a temperature characteristic identical to that of the phototransistor and having a fixed electrical state, an analog-to-digital converter that converts an analog output of the pixel cell into a digital output, a correction amount computation unit that computes a correction amount for the digital output of the analog-to-digital converter based on an output of the reference cell and a reference value, and a correction unit that corrects the digital output of the analog-to-digital converter based on the correction amount.

Abstract translation: 光电转换装置包括具有光电晶体管的像素单元，具有与光电晶体管的温度特性相同的具有固定电气状态的参考晶体管的参考晶体管，转换模拟输出的模数转换器 像素单元转换为数字输出;校正量计算单元，其基于所述参考单元的输出和参考值计算所述模数转换器的数字输出的校正量，以及校正单元， 基于校正量的模数转换器的输出。

公开(公告)号：US20150171129A1

公开(公告)日：2015-06-18

申请号：US14560037

申请日：2014-12-04

Applicant: Katsuyuki Sakurano ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Kazuhiro Yoneda ,  Yasukazu Nakatani ,  Hirofumi Watanabe

Inventor： Katsuyuki Sakurano ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Kazuhiro Yoneda ,  Yasukazu Nakatani ,  Hirofumi Watanabe

IPC: H01L27/146 ,  H01L31/113

CPC classification number: H01L31/1136 ,  H01L27/14614 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14689

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The method includes forming a trench, in a vertical direction of a semiconductor substrate having a plurality of photoelectric converting elements arranged on the semiconductor device, at positions between the photoelectric converting elements that are next to each other, forming a first conductive-material layer in and above the trench by implanting a first conductive material into the trench after an oxide film is formed on an inner wall of the trench, forming a first conductor by removing the first conductive-material layer excluding a first conductive portion of the first conductive-material layer implanted into the trench, and forming an upper gate electrode above the first conductor, the upper gate electrode configured to be conductive with the first conductor. The semiconductor device includes a semiconductor substrate, an image sensor, a trench, a first conductor, and an upper gate electrode.

Abstract translation: 公开了半导体器件和制造半导体器件的方法。 该方法包括在彼此相邻的光电转换元件之间的位置处形成在具有布置在半导体器件上的多个光电转换元件的半导体衬底的垂直方向上形成沟槽，形成第一导电材料层 并且在沟槽的内壁上形成氧化膜之后，通过将第一导电材料注入到沟槽中并在沟槽之上形成第一导体，通过除去除第一导电材料的第一导电部分之外的第一导电材料层 层，并且在第一导体上形成上栅电极，上栅电极被配置为与第一导体导电。 半导体器件包括半导体衬底，图像传感器，沟槽，第一导体和上部栅电极。

公开(公告)号：US20150076572A1

公开(公告)日：2015-03-19

申请号：US14482092

申请日：2014-09-10

Applicant: Katsuyuki Sakurano ,  Hirobumi Watanabe ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Kazuhiro Yoneda

Inventor： Katsuyuki Sakurano ,  Hirobumi Watanabe ,  Takaaki Negoro ,  Katsuhiko Aisu ,  Kazuhiro Yoneda

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of photoelectric conversion elements arranged on the semiconductor substrate to collectively form an image sensor, a plurality of trenches each formed between the photoelectric conversion elements adjacent to each other, and a plurality of impurity diffusion layers each provided at a bottom of the trench at a position deeper than a p-n junction of the photoelectric conversion element.

Abstract translation: 半导体器件包括半导体衬底，布置在半导体衬底上以共同形成图像传感器的多个光电转换元件，各自形成在彼此相邻的光电转换元件之间的多个沟槽，以及多个杂质扩散层 设置在比光电转换元件的pn结更深的位置处的沟槽的底部。

公开(公告)号：US20130234277A1

公开(公告)日：2013-09-12

申请号：US13793445

申请日：2013-03-11

Applicant: Takaaki Negoro ,  Hirofumi Watanabe ,  Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune

Inventor： Takaaki Negoro ,  Hirofumi Watanabe ,  Yutaka Hayashi ,  Toshitaka Ota ,  Yasushi Nagamune

IPC: H01L27/146 ,  H01L29/73

CPC classification number: H01L27/14681 ,  H01L27/14683 ,  H01L29/73 ,  H01L29/739 ,  H01L31/1105

Abstract: The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode.

Abstract translation: 本发明涉及一种半导体器件，其具有从半导体衬底表面沿深度方向依次形成的发射极，基极和集电极的垂直晶体管双极结构。 半导体器件包括从半导体衬底表面嵌入内部并由氧化物膜绝缘的电极。 在基板的表面中，从第一导电型第一半导体区域，第二导电型第二半导体区域和第一导电型第三半导体区域的表面侧配置在半导体器件区域 被电极围绕并且沿着电极，氧化膜插入其间，位于第一半导体区域下方的第二半导体区域，位于第二半导体区域下方的第三半导体区域。 电极与第一至第三半导体区域绝缘​​，电流增益可通过向电极施加电压而变化。