公开(公告)号：US06528327B2

公开(公告)日：2003-03-04

申请号：US09922782

申请日：2001-08-07

申请人： Yoshihisa Nagano ,  Toru Nasu ,  Hajime Yasuoka ,  Eiji Fujii

发明人： Yoshihisa Nagano ,  Toru Nasu ,  Hajime Yasuoka ,  Eiji Fujii

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L28/60 ,  H01L28/91

摘要： A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.

摘要翻译： 在通过基板上的钝化膜形成的接触孔中形成接触塞，使得凹部留在接触插塞上。 然后，钝化膜被干蚀刻，使得凹部的开口膨胀或凹陷的深度减小。 之后，依次形成与触点插头连接的下部电极，绝缘金属氧化物的电容绝缘膜和上部电极，制成电容器。

公开(公告)号：US06294438B1

公开(公告)日：2001-09-25

申请号：US09589520

申请日：2000-06-08

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

摘要翻译： 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US6107657A

公开(公告)日：2000-08-22

申请号：US71121

申请日：1998-05-04

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/72

CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

摘要翻译： 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US5837591A

公开(公告)日：1998-11-17

申请号：US803144

申请日：1997-02-19

申请人： Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

发明人： Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L21/20

CPC分类号： H01L27/11502 ,  H01L28/40

摘要： A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.

摘要翻译： 半导体器件包括其上形成有集成电路的硅衬底1，形成在硅衬底1上的第一绝缘层6，包括形成在第一绝缘层6上的下电极7的电容器，具有高介电常数的电介质膜8和上电极9 具有独立地引导到下电极7和上电极9的接触孔13的第二绝缘膜11，在接触孔13的底部接触下电极7和上电极9的扩散阻挡层17和形成在扩散阻挡层上的互连层15 在接触孔13的底部的扩散阻挡层17中，形成由粒状晶体构成的层状区域。

公开(公告)号：US5591663A

公开(公告)日：1997-01-07

申请号：US388502

申请日：1995-02-14

申请人： Toru Nasu ,  Atsuo Inoue ,  Yoshihisa Nagano ,  Akihiro Matsuda ,  Koji Arita

发明人： Toru Nasu ,  Atsuo Inoue ,  Yoshihisa Nagano ,  Akihiro Matsuda ,  Koji Arita

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11502

摘要： A manufacturing method of a semiconductor device comprises the steps:(a) forming a ferroelectric capacitor on a semiconductor substrate on which a MOS transistor is formed, (b) forming an interlayer insulating film which covers the whole semiconductor substrate, (c) forming first contact holes which reach diffusion layers of the MOS transistor, (d) after forming the first contact holes, providing a heat treatment in hydrogen atmosphere, (e) after the heat treatment, forming second contact holes which reach upper and lower electrodes of the ferroelectric capacitor on the interlayer insulating film, and (f) forming metal interconnection. Since the heat treatment in hydrogen atmosphere is provided before forming the second contact holes, a surface state density at interface between the semiconductor and a gate insulating film of the MOS transistor can be lowered without degrading the characteristics of ferroelectric capacitor.

摘要翻译： 半导体器件的制造方法包括以下步骤：（a）在形成有MOS晶体管的半导体衬底上形成强电介质电容器，（b）形成覆盖整个半导体衬底的层间绝缘膜，（c） 接触孔到达MOS晶体管的扩散层，（d）在形成第一接触孔之后，在氢气氛中进行热处理，（e）在热处理之后，形成到铁电体的上下电极的第二接触孔 层间绝缘膜上的电容器，（f）形成金属互连。 由于在形成第二接触孔之前提供氢气氛中的热处理，所以可以降低MOS晶体管的半导体与栅极绝缘膜之间的界面处的表面状态密度，而不降低铁电电容器的特性。

公开(公告)号：US20060292816A1

公开(公告)日：2006-12-28

申请号：US11415069

申请日：2006-05-02

申请人： Takumi Mikawa ,  Toru Nasu

发明人： Takumi Mikawa ,  Toru Nasu

IPC分类号： H01L21/20 ,  H01L29/00

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/91

摘要： A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating film of a dielectric film formed on wall and bottom portions of the second recess and having a third recess, and a capacitor upper electrode formed on wall and bottom portions of the third recess; and a conductive layer (referred hereinafter to as a low-resistance conductive layer) which is formed to cover at least portions of the respective capacitor upper electrodes constituting the plurality of capacitor elements and to extend across the plurality of capacitor elements and which has a lower resistance than the capacitor upper electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底上并具有第一凹槽的绝缘膜; 多个电容器元件，每个电容器元件由形成在第一凹部的壁和底部上的电容器下电极组成，并具有第二凹部，形成在第二凹部的壁和底部上的电介质膜的电容绝缘膜， 具有第三凹部和形成在第三凹部的壁部和底部上的电容器上电极; 以及形成为覆盖构成多个电容器元件的各个电容器上电极的至少一部分并且跨越多个电容器元件并且具有较低电容器元件的导电层（以下称为低电阻导电层） 电阻比电容器上电极。

公开(公告)号：US20060026250A1

公开(公告)日：2006-02-02

申请号：US11192732

申请日：2005-07-29

申请人： Takayuki Ito ,  Hidenori Miyamoto ,  Toru Nasu ,  Shikiko Kawano

发明人： Takayuki Ito ,  Hidenori Miyamoto ,  Toru Nasu ,  Shikiko Kawano

IPC分类号： G06F15/16

CPC分类号： H04L51/22 ,  H04L51/30

摘要： When a mail server 31 and a mail server 32 are in a failover state, switches 21, 22 select communication paths E, F. A temporary save server 50 stores email received from a mail reception server 10 during the failover in a disk storage 60, and after the completion of the failover, transmits to a mail server (e.g., mail server 32) that has been switched to function as a primary system an email stored in disk storage 60 and a write request for a disk storage 40. Mail server 32, upon receiving an email and a write request from temporary save server 50, stores the received email to disk storage 40 to update stored content.

摘要翻译： 当邮件服务器31和邮件服务器32处于故障转移状态时，交换机21,22选择通信路径E，F。临时保存服务器50将在故障切换期间从邮件接收服务器10接收的电子邮件存储在磁盘存储器60中， 并且在完成故障转移之后，将已经被切换为用作主系统的邮件服务器（例如，邮件服务器32）存储在磁盘存储器60中的电子邮件和对磁盘存储器40的写入请求。 邮件服务器32在接收到来自临时保存服务器50的电子邮件和写入请求时，将接收的电子邮件存储到磁盘存储器40以更新存储的内容。

公开(公告)号：US06756621B2

公开(公告)日：2004-06-29

申请号：US10330160

申请日：2002-12-30

申请人： Toru Nasu ,  Shinichiro Hayashi

发明人： Toru Nasu ,  Shinichiro Hayashi

IPC分类号： H01L31119

CPC分类号： H01L28/56

摘要： The ferroelectric capacitor device includes a bottom electrode, a capacitor insulating film formed of a ferroelectric film, and a top electrode. The ferroelectric film has a bismuth layer structure including a plurality of bismuth oxide layers and a plurality of perovskite-like layers alternately put on top of each other. The plurality of bismuth oxide layers are formed of Bi2O2, and the plurality of perovskite-like layers include two or more kinds of layers represented by a general formula: Am−1BmO3m+&agr; (where A is a univalent, divalent or trivalent metal, B is a tetravalent, pentavalent or hexavalent metal, m is an integer equal to or more than 1, at least one of A being Bi if m is an integer of 2 or more, and 0≦&agr;≦1) and different in the value of m.

摘要翻译： 铁电电容器装置包括底电极，由铁电体膜形成的电容绝缘膜和顶电极。 铁电体膜具有包括多个氧化铋层和交替放置在彼此顶部的多个钙钛矿层的铋层结构。 多个氧化铋层由Bi 2 O 2形成，多个钙钛矿层包含由以下通式表示的两种或更多种层：Am-1BmO3m +α（其中A为一价，二价或三价金属，B 是四价，五价或六价金属，m是等于或大于1的整数，如果m是2或更大的整数，并且0≤α≤1，则A中的至少一个是Bi，并且在 值m。

公开(公告)号：US06734456B2

公开(公告)日：2004-05-11

申请号：US10287824

申请日：2002-11-05

申请人： Keisuke Tanaka ,  Toru Nasu ,  Masamichi Azuma

发明人： Keisuke Tanaka ,  Toru Nasu ,  Masamichi Azuma

IPC分类号： H01L2976

CPC分类号： H01L21/02197 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/75

摘要： The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0

摘要翻译： 本发明的铁电体膜由通式Bi4-x + yAxTi3O12或（Bi4-x + yAxTi3O12）z +（DBi2E2O9）1-z表示的铁电材料制成，其中A为选自 La，Pr，Nd，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb，Lu和V; D是选自Sr，Ba，Ca，Bi，Cd，Pb和La的元素; E是选自Ti，Ta，Hf，W，Nb，Zr和Cr的元素; 0 <= x <= 2,0

公开(公告)号：US06528365B2

公开(公告)日：2003-03-04

申请号：US09974510

申请日：2001-10-10

申请人： Yoshihisa Nagano ,  Keisuke Tanaka ,  Toru Nasu

发明人： Yoshihisa Nagano ,  Keisuke Tanaka ,  Toru Nasu

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/40

摘要： A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and the lower electrodes.