公开(公告)号：US5193186A

公开(公告)日：1993-03-09

申请号：US647754

申请日：1991-01-30

Applicant: Yoshiko Tamaki ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshikazu Tanaka

Inventor： Yoshiko Tamaki ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshikazu Tanaka

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177

CPC classification number: G06F9/52

Abstract: In a processor system for executing a plurality of tasks, which respectively control execution of one or more of a plurality of processes, a method of restarting execution of a first process which is under control of a specific task being executed, after the first process is stopped to wait for occurrence of an event associated with at least one second process different from the first process, includes the steps of (a) detecting whether or not the event associated with the second process has occurred; (b) restarting the execution of the first process when it is detected that the event has occurred; (c) determining whether or not there is an execution waiting process when the event has not yet occurred; (d) executing an executing waiting process when there is any; and (e) repeating the steps (a) to (d) after execution of an execution waiting process when there is any or after the step (c) when there is not such an execution waiting process.

Abstract translation: 在用于执行分别控制多个处理中的一个或多个处理的执行的多个任务的处理器系统中，在第一处理之后重新启动正在执行的特定任务正在执行的第一进程的执行的方法 停止等待与与第一处理不同的至少一个第二进程相关联的事件的发生，包括以下步骤：（a）检测与第二进程相关联的事件是否已经发生; （b）当检测到事件发生时重新启动第一进程的执行; （c）当事件尚未发生时确定是否存在执行等待处理; （d）当有任何时候执行执行的等待进程; 以及（e）当在没有这样的执行等待处理时存在步骤（c）之后或之后执行执行等待处理之后，重复步骤（a）至（d）。

公开(公告)号：US4803620A

公开(公告)日：1989-02-07

申请号：US445

申请日：1987-01-05

Applicant: Yasuhiro Inagami ,  Takayuki Nakagawa ,  Shigeo Nagashima

Inventor： Yasuhiro Inagami ,  Takayuki Nakagawa ,  Shigeo Nagashima

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/52 ,  G06F15/163 ,  G06F15/177 ,  G06F15/78 ,  G06F17/16 ,  G06F9/30

CPC classification number: G06F15/8076 ,  G06F9/30036 ,  G06F9/3877

Abstract: A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The slave processor also operates to set at the indicator an indication instruction indicating completion of execution of the succedding instruction. The master processor functions to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.

Abstract translation: 一种多处理器系统，包括用于存储指令和数据的主存储器，用于向从处理器提供由从处理器执行的处理所需的数据的主处理器以及命令启动处理，主处理器进一步操作以测试 从属处理器的操作状态，并利用从属处理器执行的处理结果来执行处理。 从处理器在主处理器的命令下启动处理，并且操作以通知主处理器完成处理。 从处理器操作以执行暂停指令，暂停对后续指令的处理的暂时激活，并在从属处理器的指示器处设置暂停指示。 当在从属处理器中设置暂停指示时，主处理器操作以复位该指示，以使从属处理器从暂停状态释放。 当暂停状态指示未设置时，主处理器执行从主存储器提供的清除指令，以暂停用于激活后续指令的功能。 从处理器还用于在指示器处设置指示完成执行完成指令的指示。 主处理器用于重置在从属处理器处的指令集的完成执行的指示，否则执行用于暂停后续指令的激活的指示复位指令。

公开(公告)号：US4768146A

公开(公告)日：1988-08-30

申请号：US859373

申请日：1986-05-05

Applicant: Shigeo Nagashima ,  Koichiro Omoda ,  Yasuhiro Inagami

Inventor： Shigeo Nagashima ,  Koichiro Omoda ,  Yasuhiro Inagami

IPC: G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  G06F17/16 ,  G06F9/00

CPC classification number: G06F15/8061 ,  G06F12/1027

Abstract: A unit operative in concurrence with a vector processing for beforehand sequentially generating page addresses containing vector data to be referred to thereafter and a unit for achieving a processing to determine whether or not a page fault occurs in a page in an address translation and responsive to an occurrence of a page fault in a page for executing processing to beforehand transfer the page to a main storage are provided. Even if a vector element existing in the page becomes necessary in the vector processing after the operation described above, another paging processing is not necessary because the page exists in the main storage.

Abstract translation: 一种与矢量处理一致的单元，用于预先顺序地生成包含以后要参考的矢量数据的页地址，以及用于实现处理的单元，以确定在地址转换中的页面中是否发生页面错误，并响应于 提供了用于执行预先将页面传送到主存储器的处理的页面中的页面错误的发生。 即使在上述操作之后的矢量处理中存在页面中的矢量元素也是必要的，因为页面存在于主存储器中，所以不需要另外的寻呼处理。

公开(公告)号：US4488247A

公开(公告)日：1984-12-11

申请号：US366325

申请日：1982-04-07

Applicant: Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Shunichi Torii

Inventor： Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Shunichi Torii

IPC: G06F7/483 ,  G06F7/508 ,  G06F7/52 ,  G06F7/525 ,  G06F7/527 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/3884 ,  G06F2207/5355 ,  G06F7/49942

Abstract: An approximate quotient-correcting circuit wherein an approximate quotient Q.sub.H, a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q.sub.H and the divisor D are multiplied; it is decided whether the lower m digits of Q.sub.H .times.D are not all `0` and whether the m-th significant bit of Q.sub.H .times.D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q.sub.H -2.sup.-m is provided as a quotient.

Abstract translation: 一个近似商校正电路，其中读出一个近似商QH，一个除数D和一个除数N的分数部分的最低有效位; 乘数近似商QH和除数D; 确定QHxD的较低m位不是全为“0”，QHxD的第m个有效位是否与N的第m个有效位一致; 当决定结果为正时，提供QH-2-m作为商。

公开(公告)号：US06502136B1

公开(公告)日：2002-12-31

申请号：US09846261

申请日：2001-05-02

Applicant: Tatsuo Higuchi ,  Toshiaki Tarui ,  Katsuyoshi Kitai ,  Shigeo Takeuchi ,  Tatsuru Toba ,  Machiko Asaie ,  Yasuhiro Inagami

Inventor： Tatsuo Higuchi ,  Toshiaki Tarui ,  Katsuyoshi Kitai ,  Shigeo Takeuchi ,  Tatsuru Toba ,  Machiko Asaie ,  Yasuhiro Inagami

IPC: G06F1300

CPC classification number: G06F9/52 ,  G06F15/17381 ,  H04L45/06

Abstract: A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each processing node for storing in parallel use status information indicating whether the resource is in exclusive use status. The computer system includes a plurality of request issue circuits, each being provided in each processing node, for issuing requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to the processing nodes and a plurality of status control circuits. Each status control circuit is provided in each processing node to update a corresponding register set depending on use status information and each request received at a corresponding node.

Abstract translation: 一种包括多个处理节点的计算机系统，提供给任何处理节点使用的至少一个资源和多个寄存器组。 在每个处理节点中提供每个寄存器组，用于并行地存储指示资源是否处于独占状态的状态信息。 计算机系统包括多个请求发布电路，每个请求发布电路各设置在每个处理节点中，用于发出专用资源的请求;消息交换电路，用于将由请求发布电路发出的请求串行化为串行化顺序，并且广播请求 到处理节点和多个状态控制电路。 在每个处理节点中提供每个状态控制电路，以根据使用状态信息和在相应节点处接收到的每个请求来更新对应的寄存器集。

公开(公告)号：US5729723A

公开(公告)日：1998-03-17

申请号：US275347

申请日：1994-07-15

Applicant: Hideo Wada ,  Katsumi Takeda ,  Yasuhiro Inagami ,  Hiroaki Fujii

Inventor： Hideo Wada ,  Katsumi Takeda ,  Yasuhiro Inagami ,  Hiroaki Fujii

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46 ,  G06F3/00

CPC classification number: G06F9/381 ,  G06F9/30101 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/462

Abstract: A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.

Abstract translation: 一种数据处理单元，其可以访问比通过用于实现程序的高速执行的指令可寻址的寄存器的更多数量的寄存器。 为此，数据处理单元包括比通过普通指令寻址的寄存器数量更多的浮点寄存器，窗口开始指针寄存器，窗口起始指针有效寄存器，转换电路，当窗口起始指针有效时 寄存器的值为1，用于将指令中的浮点寄存器号转换为物理浮点寄存器号，并根据窗口开始指针寄存器的值改变转换模式;窗口开始指针集指令，用于设置 窗口开始指针寄存器的值，以及具有与普通指令长度不同的寄存器字段的浮点寄存器预加载和后存储指令，并且其中由寄存器字段指定的浮点寄存器号由转换电路 基于窗口起始指针寄存器的值，到物理浮点寄存器号。

公开(公告)号：US5506980A

公开(公告)日：1996-04-09

申请号：US964845

申请日：1992-10-22

Applicant: Yasuhiro Inagami ,  Yoshiko Tamaki ,  Katsuyoshi Kitai ,  Teruo Tanaka ,  Tadayuki Sakakibara

Inventor： Yasuhiro Inagami ,  Yoshiko Tamaki ,  Katsuyoshi Kitai ,  Teruo Tanaka ,  Tadayuki Sakakibara

IPC: G06F15/173 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F15/17368

Abstract: In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.

Abstract translation: 在具有多个主存储器和共享扩展存储器的多处理器系统中，每个主存储器与扩展存储器部分写入控制相关联。 当发出扩展存储器部分写入指令时，识别主存储器数据的更新部分的标签信息与主存储器数据一起传送到相关联的扩展存储器部分写入控制。 每当主存储器数据的子块到达时，扩展存储器部分写入控制执行部分写入操作，以将由标签信息识别的主存储器数据的那些部分替换为指定扩展中的数据子块的对应部分 记忆区。 在该部分写入操作期间，指定的扩展内存区域被保持锁定。

公开(公告)号：US5392443A

公开(公告)日：1995-02-21

申请号：US855056

申请日：1992-03-19

Applicant: Tadayuki Sakakibara ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshiko Tamaki ,  Teruo Tanaka ,  Tadaaki Isobe ,  Shigeko Yazawa ,  Masanao Ito

Inventor： Tadayuki Sakakibara ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshiko Tamaki ,  Teruo Tanaka ,  Tadaaki Isobe ,  Shigeko Yazawa ,  Masanao Ito

IPC: G06F12/06 ,  G06F15/78 ,  G06F15/16

CPC classification number: G06F15/8076 ,  G06F12/0607

Abstract: A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.

Abstract translation: 在存储控制单元部分中采用多个存储控制单元; 此外，与这些存储控制单元相关联地采用两个请求者模块。 每个存储器模块由与存储控制单元一样多的存取组组构成。 访问存储组以并行方式操作，并且可以从任何一个存储控制单元访问。 在元素分配中，每个请求者模块中的多个请求控制单元和每个向量寄存器单元中的多个向量数据控制器分别被分配从零开始的序列号。 对于矢量数据控制器，分配给它的数字被请求模块计数除以获得余数，使得矢量数据控制器被分配给具有与其余值相同数目的请求模块。 此外，请求队列设置在每个优先级单元之前的阶段，并且请求发送单元被布置为在其中存储请求队列的状态并且控制来自每个请求控制单元的请求传输。 根据分别适合的偏移方案将地址分配给相应的存储器模块，存储体组和存储体。

公开(公告)号：US4825361A

公开(公告)日：1989-04-25

申请号：US21590

申请日：1987-03-02

Applicant: Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

Inventor： Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

IPC: G06F17/16 ,  G06F15/78 ,  G06F15/347

CPC classification number: G06F15/8076

Abstract: A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

Abstract translation: 一种矢量处理器，具有由12位字节大小的元素构成的向量寄存器，用于存储由从具有多个存储区域的主存储器读出的多个元素组成的矢量数据，并且能够读出l1- 字节大小从指定的地址限制开始，并适用于顺序地向向量寄存器中写入具有m（l1 / m为整数，l2大于或等于m）的元素大小的向量数据，从 向量寄存器，用于由算术单元计算，并将计算结果写入向量寄存器，其中处理器以从后续操作所需的顺序将从主存储器读出的向量数据的元素写入分离的向量寄存器的指定位置。

公开(公告)号：US4541046A

公开(公告)日：1985-09-10

申请号：US361478

申请日：1982-03-23

Applicant: Shigeo Nagashima ,  Shunichi Torii ,  Koichiro Omoda ,  Yasuhiro Inagami

Inventor： Shigeo Nagashima ,  Shunichi Torii ,  Koichiro Omoda ,  Yasuhiro Inagami

IPC: G06F9/38 ,  G06F15/78 ,  G06F15/31

CPC classification number: G06F9/3887 ,  G06F15/8061 ,  G06F9/30036 ,  G06F9/3879

Abstract: A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.

Abstract translation: 矢量处理器包括用于存储用于执行期望操作的标量指令链和矢量指令链的主存储器，以及用于分别取出标量指令链和向量指令链的标量处理单元和向量处理单元，对它们进行解码并执行它们 标量处理和向量处理以重叠的方式执行。