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62 条记录 (耗时 0.025 秒)

    Nonvolatile semiconductor memory with pre-read means
    21.
    发明授权
    Nonvolatile semiconductor memory with pre-read means 失效
    具有预读功能的非易失性半导体存储器

    公开(公告)号：US5572463A

    公开(公告)日：1996-11-05

    申请号：US416281

    申请日：1995-04-04

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group of data pieces according the another address to be provided by the first address generation means while the preceding data pieces are being read according to the preceding address provided by the first address generation means and being selectively provided to the output buffer according to the addresses provided by the second address generation means.

    摘要翻译： 具有地址缓冲器装置，存储单元装置，字线选择装置，位线选择装置，输出缓冲器，连接到地址缓冲器装置的第一地址产生装置的半导体存储器，用于提供和寻址用于指定一组数据片段，以及 第二地址产生装置，分别提供用于指定数据片段的地址，所述半导体存储器包括第一读取装置，用于根据由字线选择装置和位线选择装置中的一个选择和读取一组数据片段， 第一地址产生装置，用于根据由第一地址产生装置提供的地址选择和读取的数据片段的第二地址产生装置，通过位线选择装置和字线选择装置之一，根据由 第二地址产生装置并将其提供给输出缓冲器; 以及预读取装置，用于根据由第一地址产生装置提供的另一地址读取另一组数据片段，同时根据由第一地址产生装置提供的先前地址读取先前的数据，并且选择性地提供给 所述输出缓冲器根据由所述第二地址产生装置提供的地址。

    Body-bias voltage controller and method of controlling body-bias voltage
    22.
    发明授权
    Body-bias voltage controller and method of controlling body-bias voltage 有权
    车身偏置电压控制器和控制体偏置电压的方法

    公开(公告)号：US08659346B2

    公开(公告)日：2014-02-25

    申请号：US12835732

    申请日：2010-07-13

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G05F1/10

    CPC分类号： G05F3/205

    摘要： A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

    摘要翻译： 体偏置电压控制器包括：多个晶体管，其中至少一个被提供有体偏置电压; 监视电路，用于检测多个晶体管的电压特性并输出指示信号; 以及体偏置电压发生器，用于基于指示信号产生体偏置电压。

    Level shift circuit and semiconductor device
    23.
    发明授权
    Level shift circuit and semiconductor device 有权
    电平移位电路和半导体器件

    公开(公告)号：US08542051B2

    公开(公告)日：2013-09-24

    申请号：US13218154

    申请日：2011-08-25

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： H03L5/00

    CPC分类号： H03K3/35613 ,  H03K2217/0018

    摘要： A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.

    摘要翻译： 一种电平移位电路，包括电平转换单元，其将具有第一电压的信号电平的输入信号转换为具有高于第一电压的第二电压的信号电平的信号。 电平转换单元包括第一导电类型的第一和第二MOS晶体管和第二导电类型的第三和第四MOS晶体管，其与第一导电类型不同，并且根据输入信号来控制开关。 第三和第四MOS晶体管分别包括经由第一和第二MOS晶体管提供有第二电压的漏极。 控制单元当检测到第一电压的降低时，控制第三和第四MOS晶体管的体偏置以降低第三和第四MOS晶体管的阈值电压。

    Semiconductor device having logic circuit and macro circuit
    24.
    发明授权
    Semiconductor device having logic circuit and macro circuit 有权
    具有逻辑电路和宏电路的半导体器件

    公开(公告)号：US07167042B2

    公开(公告)日：2007-01-23

    申请号：US10757395

    申请日：2004-01-15

    申请人： Yasushige Ogawa ,  Yoshiyuki Ishida

    发明人： Yasushige Ogawa ,  Yoshiyuki Ishida

    IPC分类号： G05F3/02

    CPC分类号： G11C29/12005 ,  G11C7/1006 ,  G11C7/22 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/5006 ,  G11C2207/2227

    摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

    摘要翻译： 半导体器件包括逻辑电路和宏电路。 宏电路包括消耗直流（DC）电路。 为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。 宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

    Method and program for designing semiconductor device
    26.
    发明申请
    Method and program for designing semiconductor device 有权
    设计半导体器件的方法和程序

    公开(公告)号：US20060123366A1

    公开(公告)日：2006-06-08

    申请号：US11097204

    申请日：2005-04-04

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5036 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    摘要： It is an object of the present invention to provide a semiconductor device design method and program that can rapidly improve power supply noise characteristics and reduce the noise sufficiently without being restricted in design and noise solution. A step of performing frequency analysis on a power supply distribution network model creates a power supply distribution network model based on electric characteristics obtained in accordance with specifications (maximum allowable drop value of power supply voltage, power supply current value, operating frequency, etc.) of the semiconductor device and performs frequency analysis on this power supply distribution network model. A step of performing frequency analysis based on an operating current waveform analyzes power supply current characteristics based on an operating current waveform obtained in accordance with the specification. A step of calculating power supply noise calculates the power supply noise in accordance with analysis results of the step of performing frequency analysis on the power supply distribution network model and the step of performing frequency analysis based on the operating current waveform. It is thus possible to estimate the power supply noise before designing a circuit of the semiconductor device.

    摘要翻译： 本发明的一个目的是提供一种半导体器件的设计方法和程序，其可以在不受设计和噪声解决方案的限制的情况下，迅速地提高电源噪声特性并减少噪声。 在电源分配网络模型上执行频率分析的步骤基于根据规格获得的电特性（电源电压的最大允许下降值，电源电流值，工作频率等）创建电力分配网络模型， 并对该电源分配网络模型进行频率分析。 基于工作电流波形执行频率分析的步骤基于根据说明书获得的工作电流波形来分析电源电流特性。 计算电源噪声的步骤根据对电源分配网络模型进行频率分析的步骤的分析结果和基于工作电流波形执行频率分析的步骤来计算电源噪声。 因此，可以在设计半导体器件的电路之前估计电源噪声。

    Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device
    27.
    发明授权
    Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 失效
    半导体集成电路器件及半导体集成电路器件的调整方法

    公开(公告)号：US06943616B2

    公开(公告)日：2005-09-13

    申请号：US10648272

    申请日：2003-08-27

    申请人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

    发明人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

    IPC分类号： H01L27/04 ,  G01R31/3167 ,  H01L21/822 ,  H03M1/10 ,  H03M1/66 ,  G05F1/10

    CPC分类号： H03M1/1019 ,  G01R31/3167 ,  H03M1/66

    摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

    摘要翻译： 本发明旨在提供一种半导体集成电路装置的半导体集成电路装置和调整方法，能够调整从内置的模拟信号生成部输出的模拟信号而不将其输出为模拟值。 从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。 模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。 判断信号JG作为内部信号作用在预定信号存储部分4上，并且将调整信号AD提取到预定信号存储部分4中。 此外，判断信号JG通过外部端子T 2作为数字信号输出，外部测试装置获取调整信号，并将取得的调整信号存储在规定的信号存储部4中。 因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置并且根据简单的测试方法准确而快速地执行调整测试。

    Semiconductor integrated circuit device and data writing method therefor
    29.
    发明授权
    Semiconductor integrated circuit device and data writing method therefor 失效
    半导体集成电路器件及其数据写入方法

    公开(公告)号：US06741518B2

    公开(公告)日：2004-05-25

    申请号：US10005345

    申请日：2001-12-07

    申请人： Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

    发明人： Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

    IPC分类号： G11C800

    CPC分类号： G11C7/1078 ,  G11C7/12

    摘要： Provided is a semiconductor integrated circuit device capable of, when data is written into a memory cell, fixing adjacent complimentary bit lines to a predetermined voltage, thereby reducing an effect of a write noise for a readout operation of the adjacent cells, making it possible to ensure stable operation. An address signal is inputted to a bit line short signal circuit and a column switch signal circuit, and the corresponding bit line short signal BRS0 or BRS1 and column switch signal CL01 or CL11 are selected. Complimentary bit lines /BL1, /BL2 or bit lines BL1 and BL2 in which a memory cell is not connected according to the bit line short signals BRS0 and BRS1 are selected altogether, these bit lines are fixed to a precharge voltage VPR, and a write noise is shielded. The column switch signal CL01 or CL11 makes conductive the corresponding column switches, and the selected bit line BL1, BL2, /BL1, or /BL2 is connected to a data bus DB or /DB.

    摘要翻译： 提供一种半导体集成电路器件，当将数据写入存储单元时，能够将相邻的互补位线固定到预定电压，从而减少对相邻单元的读出操作的写入噪声的影响，使得可以 确保运行稳定。 地址信号输入到位线短信号电路和列切换信号电路，并选择对应的位线短信号BRS0或BRS1以及列切换信号CL01或CL11。 选择根据位线短信号BRS0和BRS1不连接存储单元的空白位线/ BL1，/ BL2或位线BL1和BL2，这些位线被固定为预充电电压VPR，写入 噪音被屏蔽。 列开关信号CL01或CL11使相应的列开关导通，并且所选位线BL1，BL2，/ BL1或/ BL2连接到数据总线DB或/ DB。

    Semiconductor memory device with redundancy circuit
    30.
    发明授权
    Semiconductor memory device with redundancy circuit 有权

    公开(公告)号：US06542421B2

    公开(公告)日：2003-04-01

    申请号：US09968609

    申请日：2001-10-02

    申请人： Hiroyuki Sugamoto ,  Yasushige Ogawa

    发明人： Hiroyuki Sugamoto ,  Yasushige Ogawa

    IPC分类号： G11C700

    CPC分类号： G11C29/848

    摘要： This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.