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59 条记录 (耗时 0.028 秒)

    LEAK CURRENT DETECTION CIRCUIT, BODY BIAS CONTROL CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING METHOD
    1.
    发明申请
    LEAK CURRENT DETECTION CIRCUIT, BODY BIAS CONTROL CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING METHOD 有权
    漏电流检测电路，体位偏置控制电路，半导体器件和半导体器件测试方法

    公开(公告)号：US20100026335A1

    公开(公告)日：2010-02-04

    申请号：US12576670

    申请日：2009-10-09

    申请人： Kiyonaga Fujii ,  Yasushige Ogawa

    发明人： Kiyonaga Fujii ,  Yasushige Ogawa

    IPC分类号： G01R31/26 ,  H01H31/12

    CPC分类号： G01R31/2621 ,  G01R31/2884 ,  G01R31/3008 ,  G01R31/3012

    摘要： A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

    摘要翻译： 一种泄漏电流检测电路，其提高了在不增加电路规模的情况下检测MOS晶体管中的漏电流的精度。 泄漏电流检测电路包括耦合到高电位电源的至少一个P沟道MOS晶体管，其通常是非激活的并且产生第一漏电流，至少一个N沟道MOS晶体管耦合在低电位 功率和至少一个P沟道MOS晶体管，并且其通常被非激活并产生第二漏电流;以及检测器，其检测在所述至少一个P沟道MOS晶体管和所述至少一个N之间的节点处产生的电位 - 沟道MOS晶体管，根据第一和第二漏电流。

    Control apparatus, semiconductor integrated circuit apparatus, and source voltage supply control system
    2.
    发明授权
    Control apparatus, semiconductor integrated circuit apparatus, and source voltage supply control system 有权
    控制装置，半导体集成电路装置和源电压供给控制系统

    公开(公告)号：US07557587B2

    公开(公告)日：2009-07-07

    申请号：US11723599

    申请日：2007-03-21

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G01R27/02 ,  G01R31/02 ,  G01R31/26

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： An excluding unit is controlled by a control signal received from a control unit, and based on the control signal a determination is made for each of circuit blocks as to whether either a voltage signal at a position of its corresponding circuit block or a signal indicating a voltage is outputted to a selection unit. From a circuit block which is not in operation, the voltage, but not a voltage signal at a position of the circuit block, is outputted to the selection unit. By this, the circuit block which is not in operation cannot be judged to have voltage drop, and accordingly, a high supply voltage cannot be supplied. Consequently, a malfunction caused by supply voltages to other circuit blocks being too high does not occur.

    摘要翻译： 排除单元由从控制单元接收到的控制信号控制，并且基于控制信号，确定每个电路块是关于其相应电路块的位置处的电压信号还是指示相应电路块的信号 电压被输出到选择单元。 从不工作的电路块，电路块的电压而不是电压信号被输出到选择单元。 由此，不能判断不工作的电路块具有电压降，因此不能提供高电源电压。 因此，不会发生由其他电路块的电源电压引起的故障。

    Multi-power supply circuit and multi-power supply method
    3.
    发明申请
    Multi-power supply circuit and multi-power supply method 审中-公开
    多电源电路和多电源方式

    公开(公告)号：US20070001652A1

    公开(公告)日：2007-01-04

    申请号：US11431882

    申请日：2006-05-11

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G05F1/613

    CPC分类号： H02M3/1588 ,  H02M2001/0045 ,  H02M2001/008 ,  Y02B70/1466

    摘要： The present invention aims to provide a multi-power supply circuit capable of generating multi-power efficiently and reducing power consumption, and a multi-power supply method therefor. A supply voltage is output from a DCDC converter. Output transistors of linear regulators are series-connected to a power supply path between a resistive element and the DCDC converter. That is, a bias current path is shared between the linear regulators and the corresponding path is taken as one. With the supply voltage as the reference, supply voltages corresponding to intermediate negative voltages between the supply voltage and a reference voltage are generated by the linear regulators. A bias current consumed by the multi-power supply circuit is held constant as a bias current i regardless of the number of the linear regulators.

    摘要翻译： 本发明旨在提供一种能够有效地产生多功率并降低功耗的多电源电路及其多电源方式。 从DCDC转换器输出电源电压。 线性调节器的输出晶体管串联连接到电阻元件和DCDC转换器之间的电源路径。 也就是说，在线性调节器之间共享偏置电流路径，并将相应的路径视为一个。 以电源电压作为参考，电源电压和参考电压之间的中间负电压对应的电源电压由线性稳压器产生。 多极电源电路消耗的偏置电流作为偏置电流i保持不变，而与线性稳压器的数量无关。

    Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit
    5.
    发明申请
    Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit 失效
    振荡器电路，半导体器件和配有振荡电路的半导体存储器件，以及振荡电路的控制方法

    公开(公告)号：US20050030113A1

    公开(公告)日：2005-02-10

    申请号：US10943927

    申请日：2004-09-20

    申请人： Yasushige Ogawa ,  Satoru Kawamoto

    发明人： Yasushige Ogawa ,  Satoru Kawamoto

    IPC分类号： H03K3/014 ,  H03K3/03 ,  H03B1/00

    CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

    摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

    摘要翻译： 提供了一种振荡器电路，其能够通过在振荡开始时避免可能发生在操作/停止控制可行型振荡器电路的频率不稳定的输出而获得稳定的频率。 在这种振荡电路中，振荡允许信号（EN）将振荡器部分置于振荡可操作状态，由此控制器部分开始工作。 已经观察其操作的控制器部分将振荡频率控制信号（VR）改变成对应于预定振荡频率的信号值，以便在振荡器部分设置振荡频率。 此外，振荡器部分响应于在检测器部分将输入的信号与预定信号值进行比较之后输出的检测信号（MON）输出振荡信号，并检测输入信号达到预定信号值。 由此，可以检测振荡频率控制信号（VR）的瞬态。 也就是说，可以避免由于瞬态振荡频率控制信号（VR）引起的不稳定振荡​​信号的输出。

    Nonvolatile semiconductor memory
    8.
    发明授权
    Nonvolatile semiconductor memory 失效

    公开(公告)号：US5590074A

    公开(公告)日：1996-12-31

    申请号：US466732

    申请日：1995-06-06

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

    Layout method of decoupling capacitors
    9.
    发明授权
    Layout method of decoupling capacitors 有权
    去耦电容布局方法

    公开(公告)号：US07222320B2

    公开(公告)日：2007-05-22

    申请号：US11023829

    申请日：2004-12-29

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G06F17/50

    CPC分类号： H01L23/50 ,  G06F17/5072 ,  G06F17/5081 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of grid areas, arranging the logic cells in each grid area, determining whether the decoupling capacitance is sufficient in each grid area for the logic cells in that grid area, and performing a supplementing process of the decoupling capacitance based on whether the decoupling capacitance is sufficient.

    摘要翻译： 一种去耦电容器的布局方法，同时确保每个栅格区域所需的去耦电容。 该方法包括计算逻辑单元的总功耗，对应于总功耗排列整个对象区域的去耦电容，将主区划分为多个网格区域，将逻辑单元布置在每个网格区域中，确定是否 在该网格区域中的逻辑单元的每个网格区域中去耦电容就足够了，并且基于去耦电容是否足够来执行去耦电容的补充处理。

    Semiconductor device having logic circuit and macro circuit
    10.
    发明授权
    Semiconductor device having logic circuit and macro circuit 失效
    具有逻辑电路和宏电路的半导体器件

    公开(公告)号：US07078945B2

    公开(公告)日：2006-07-18

    申请号：US11045104

    申请日：2005-01-31

    申请人： Yasushige Ogawa ,  Yoshiyuki Ishida

    发明人： Yasushige Ogawa ,  Yoshiyuki Ishida

    IPC分类号： H03L7/00

    CPC分类号： G11C29/12005 ,  G11C7/1006 ,  G11C7/22 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/5006 ,  G11C2207/2227

    摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

    摘要翻译： 半导体器件包括逻辑电路和宏电路。 宏电路包括消耗直流（DC）电路。 为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。 宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。