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21.发明授权公开(公告)号：US09455040B2
公开(公告)日：2016-09-27
申请号：US14962333
申请日：2015-12-08
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Moshe Neerman , Naftali Sommer , Avraham Poza Meir , Etai Zaltsman , Eyal Gurgi , Meir Dalal
CPC classification number: G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/349
Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
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22.发明授权Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block 有权识别存储器块中的字线到基板和字线到字线的短路事件公开(公告)号：US09330783B1
公开(公告)日：2016-05-03
申请号：US14572818
申请日：2014-12-17
Applicant: APPLE INC.
Inventor： Barak Rotbard , Avraham Poza Meir , Eyal Gurgi , Yael Shur , Barak Baum
CPC classification number: G11C29/025 , G11C29/006 , G11C2029/1202
Abstract: An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.
Abstract translation: 一种装置包括存储器和存储器控制器。 该存储器包括一个包含通过字线连接的存储器单元的存储块。 存储器控制器被配置为将数据存储在存储器单元中，并且通过识别存储器块中的至少给定字线的性能特性相对于性能特性的偏差来识别存储器块中的可疑短路事件 剩余字线在存储器块中。
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23.发明授权Mitigating reliability degradation of analog memory cells during long static and erased state retention 有权在长静态和擦除状态保持期间，减轻模拟存储单元的可靠性降级公开(公告)号：US09236132B2
公开(公告)日：2016-01-12
申请号：US14249448
申请日：2014-04-10
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Moshe Neerman , Naftali Sommer , Avraham Poza Meir , Etai Zaltsman , Eyal Gurgi , Meir Dalal
CPC classification number: G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/349
Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。
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Patent Agency Ranking
24.发明申请STORAGE IN CHARGE-TRAP MEMORY STRUCTURES USING ADDITIONAL ELECTRICALLY-CHARGED REGIONS 有权使用附加电费区的充电轨迹存储结构中的存储公开(公告)号：US20150200016A1
公开(公告)日：2015-07-16
申请号：US14457380
申请日：2014-08-12
Applicant: Apple Inc.
Inventor： Arik Rizel , Avraham Poza Meir , Yael Shur , Eyal Gurgi , Barak Baum
CPC classification number: G11C16/24 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/26 , H01L27/11568 , H01L29/42328
Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
Abstract translation: 一个设备包括一个存储器和一个读/写（R / W）单元。 存储器包括耦合到公共电荷陷阱层的多个门。 R / W单元被配置为通过在公共电荷陷阱层中创建和读取一组充电区域来对存储器进行编程和读取，其中集合中的至少一个给定区域不是唯一地与 大门。
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25.发明申请MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 有权在长期静态和擦除状态下，减轻模拟记忆细胞的可靠性降低公开(公告)号：US20140355347A1
公开(公告)日：2014-12-04
申请号：US14249448
申请日：2014-04-10
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Moshe Neerman , Naftali Sommer , Avraham Poza Meir , Etai Zaltsman , Eyal Gurgi , Meir Dalal
IPC: G11C16/16
CPC classification number: G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/349
Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。
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公开(公告)号：US20140328131A1
公开(公告)日：2014-11-06
申请号：US14332650
申请日：2014-07-16
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Eyal Gurgi
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C13/0002 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32 , G11C27/005
Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.
Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 对所选字线中的存储单元进行编程的字线电压被施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。
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公开(公告)号：US20140160866A1
公开(公告)日：2014-06-12
申请号：US13709303
申请日：2012-12-10
Applicant: APPLE INC.
Inventor： Yael Shur , Yoav Kasorla , Eyal Gurgi
IPC: G11C7/00
CPC classification number: G11C27/00 , G11C7/00 , G11C13/0002 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/32 , G11C27/005
Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.
Abstract translation: 一种方法包括在与各个字线相关联的行中排列的模拟存储器单元的阵列中，读取选定字线中的第一组存储器单元，包括存储至少一个状态的一个或多个存储器单元 数组中除字线以外的所选字线。 响应于读取状态设置第二组存储器单元的读出配置。 使用读出配置读取第二组存储单元。
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公开(公告)号：US20140160865A1
公开(公告)日：2014-06-12
申请号：US13709267
申请日：2012-12-10
Applicant: APPLE INC.
Inventor： Yael Shur , Yoav Kasorla , Eyal Gurgi
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C13/0002 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32 , G11C27/005
Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.
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