公开(公告)号：US20220179654A1

公开(公告)日：2022-06-09

申请号：US17114970

申请日：2020-12-08

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

IPC: G06F9/38 ,  G06F9/30

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

公开(公告)号：US10579126B2

公开(公告)日：2020-03-03

申请号：US15308658

申请日：2015-03-13

Applicant: ARM LIMITED

Inventor： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

公开(公告)号：US10382027B2

公开(公告)日：2019-08-13

申请号：US15568174

申请日：2016-03-03

Applicant: ARM LIMITED

Inventor： Shidhartha Das ,  David Michael Bull

IPC: H03K5/1534 ,  H03K3/037

Abstract: A transition detection circuit and method of operation of such a circuit are provided, the transition detection circuit having pulse generation circuitry to receive an input signal and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry to control a property of the pulse signal dependent on a timing window indication signal. In particular, when the pulse signal is generated at least partly while the timing window indication signal is set, the pulse control circuitry controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry. In contrast, when the pulse signal is entirely generated while the timing window indication signal is cleared, the pulse control circuitry controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry. This gives rise to significant area and energy consumption savings, while still allowing reliable detection of timing errors.

公开(公告)号：US20170294222A1

公开(公告)日：2017-10-12

申请号：US15093457

申请日：2016-04-07

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  James Edward Myers ,  Pranay Prabhat ,  David Walter Flynn ,  Shidhartha Das ,  David Michael Bull

IPC: G11C11/419 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/4125

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

公开(公告)号：US09432009B2

公开(公告)日：2016-08-30

申请号：US14081900

申请日：2013-11-15

Applicant: ARM Limited

Inventor： Paul Nicholas Whatmough ,  Shidhartha Das ,  David Michael Bull

IPC: H03L7/00 ,  H03K5/135

CPC classification number: H03K5/135

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract translation: 电路延迟监视装置具有环形振荡器，具有多个延迟元件，信号转换通过环形振荡器的延迟元件传播，并且多个采样点分布在环形振荡器周围。 选择电路根据由精细采样电路产生的信号转换的当前位置的指示来选择M个转换计数器电路中的一个，其相关位置大于来自信号转换的当前位置的所述预定量。 输出产生电路然后根据由选择电路选择的转换计数器电路的采样计数值，环形振荡器内的信号转换的当前位置的指示以及相关的参考计数数据，生成参考时间段的计数指示 到参考时间段的开始。