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公开(公告)号:US20210082853A1
公开(公告)日:2021-03-18
申请号:US16573672
申请日:2019-09-17
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Yung-Sheng LIN , Chin-Li KAO , Hsu-Nan FANG
IPC: H01L23/00
Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
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公开(公告)号:US20210050273A1
公开(公告)日:2021-02-18
申请号:US16540837
申请日:2019-08-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Ya-Yu HSIEH , Chin-Li KAO , Chung-Hsuan TSAI , Chia-Pin CHEN
Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
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公开(公告)号:US20180158766A1
公开(公告)日:2018-06-07
申请号:US15884197
申请日:2018-01-30
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chien Lin CHANG CHIEN , Chin-Li KAO , Chang Chi LEE , Chih-Pin HUNG
IPC: H01L23/498 , H01L23/00 , H01L25/00 , H01L21/48
Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.
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公开(公告)号:US20170207153A1
公开(公告)日:2017-07-20
申请号:US15479074
申请日:2017-04-04
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chien Lin CHANG CHIEN , Chin-Li KAO , Chang Chi LEE , Chih-Pin HUNG
IPC: H01L23/498 , H01L25/00 , H01L23/00 , H01L21/48
CPC classification number: H01L23/49816 , H01L21/4853 , H01L23/16 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5226 , H01L23/528 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/16235 , H01L2224/16238 , H01L2224/81193 , H01L2225/06527 , H01L2225/06544 , H01L2225/06586
Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.
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公开(公告)号:US20170133311A1
公开(公告)日:2017-05-11
申请号:US15410688
申请日:2017-01-19
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chin-Li KAO , Chang-Chi LEE , Yi-Shao LAI
IPC: H01L23/498 , H01L21/48 , H01L25/065 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49838 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/3677 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5329 , H01L24/16 , H01L25/0655 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/73204 , H01L2924/00014 , H01L2924/01014 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/06 , H01L2924/07025 , H01L2924/15738 , H01L2924/15763 , H01L2924/15787 , H01L2924/15798 , H01L2924/3511 , H01L2924/35121 , H01L2224/0401
Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.
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公开(公告)号:US20150211852A1
公开(公告)日:2015-07-30
申请号:US14167786
申请日:2014-01-29
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor: Seungbae PARK , Yu-Ho HSU , Chin-Li KAO , Tai-Yuan HUANG
CPC classification number: G01C11/04 , G01B11/245 , G01B2210/56
Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.
Abstract translation: 测量设备包括机架,第一图像捕获设备,第二图像捕获设备,第三图像捕获设备和第四图像捕获设备。 其中,第一图像拍摄装置和第二图像拍摄装置捕获要被测量对象的整个图像,第三图像拍摄装置和第四图像拍摄装置捕获多个局部区域的多个局部区域 待测物体以及整个图像和局部图像并被同时捕获。
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