公开(公告)号：US11515241B2

公开(公告)日：2022-11-29

申请号：US17203512

申请日：2021-03-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K1/11

Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.

公开(公告)号：US11276620B2

公开(公告)日：2022-03-15

申请号：US16730382

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/367

Abstract: A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device.

公开(公告)号：US10741523B2

公开(公告)日：2020-08-11

申请号：US16158294

申请日：2018-10-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.

公开(公告)号：US09837352B2

公开(公告)日：2017-12-05

申请号：US15179683

申请日：2016-06-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L29/00 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81447 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US12300602B2

公开(公告)日：2025-05-13

申请号：US17991814

申请日：2022-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Meng-Wei Hsieh ,  Teck-Chong Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.

公开(公告)号：US11764311B2

公开(公告)日：2023-09-19

申请号：US17488076

申请日：2021-09-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Pin Tsai ,  Tsung-Yueh Tsai ,  Teck-Chong Lee

IPC: H01L31/02 ,  H01L25/16 ,  H01L31/0203

CPC classification number: H01L31/02002 ,  H01L25/162 ,  H01L25/165 ,  H01L25/167 ,  H01L31/0203

Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.

公开(公告)号：US11545427B2

公开(公告)日：2023-01-03

申请号：US16447839

申请日：2019-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Chien-Hua Chen ,  Teck-Chong Lee ,  Hung-Yi Lin ,  Pao-Nan Lee ,  Hsin Hsiang Wang ,  Min-Tzu Hsu ,  Po-Hao Chen

IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

公开(公告)号：US11495572B2

公开(公告)日：2022-11-08

申请号：US16932693

申请日：2020-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.

公开(公告)号：US11373967B2

公开(公告)日：2022-06-28

申请号：US16684353

申请日：2019-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee ,  Sheng-Wen Yang

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device package includes a first semiconductor device; a second semiconductor device; and a first redistribution layer disposed on the first semiconductor device and having a side wall defining an opening that exposes the first semiconductor device. The side wall of the first redistribution layer has an average surface roughness (Ra) in a range up to 2 micrometers (μm).

公开(公告)号：US10833144B2

公开(公告)日：2020-11-10

申请号：US15351265

申请日：2016-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L23/14 ,  H01L23/15 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.