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    Electrostatic discharge protection
    22.
    发明授权
    Electrostatic discharge protection 有权

    公开(公告)号：US11195826B2

    公开(公告)日：2021-12-07

    申请号：US16776680

    申请日：2020-01-30

    Applicant: Allegro MicroSystems, LLC

    Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

    IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

    Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

    ELECTROSTATIC DISCHARGE PROTECTION
    23.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20210242193A1

    公开(公告)日：2021-08-05

    申请号：US16776680

    申请日：2020-01-30

    Applicant: Allegro MicroSystems, LLC

    Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

    IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

    Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

    Patterning of a magnetoresistance structure including two hard masks
    24.
    发明授权
    Patterning of a magnetoresistance structure including two hard masks 有权

    公开(公告)号：US10566526B1

    公开(公告)日：2020-02-18

    申请号：US16122019

    申请日：2018-09-05

    Applicant: Allegro MicroSystems, LLC

    Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Paolo Campiglio ,  Sundar Chetlur

    IPC: H01L43/08 ,  H01L43/12 ,  H01L43/10

    Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.

    Multi-layer integrated circuit with enhanced thermal dissipation using back-end metal layers
    30.
    发明授权
    Multi-layer integrated circuit with enhanced thermal dissipation using back-end metal layers 有权

    公开(公告)号：US11367830B2

    公开(公告)日：2022-06-21

    申请号：US17014129

    申请日：2020-09-08

    Applicant: Allegro MicroSystems, LLC

    Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Paolo Campiglio ,  Yen Ting Liu

    IPC: H01L43/02 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

    Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

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