公开(公告)号：US11886355B2

公开(公告)日：2024-01-30

申请号：US17660797

申请日：2022-04-26

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F3/00 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42 ,  G06F9/50

CPC classification number: G06F13/105 ,  G06F9/5077 ,  G06F13/24 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

公开(公告)号：US11687462B1

公开(公告)日：2023-06-27

申请号：US17653612

申请日：2022-03-04

Applicant: Amazon Technologies, Inc.

Inventor： Michael Zuzovski ,  Ofer Naaman ,  Adi Habusha

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0871 ,  G06F9/54

CPC classification number: G06F12/084 ,  G06F9/544 ,  G06F12/0871

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

公开(公告)号：US11003616B1

公开(公告)日：2021-05-11

申请号：US15635078

申请日：2017-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Adi Habusha ,  Yaniv Shapira ,  Daniel Joseph Grey

IPC: G06F13/42 ,  G06F13/40

Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.

公开(公告)号：US10901627B1

公开(公告)日：2021-01-26

申请号：US15445324

申请日：2017-02-28

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Thomas A. Volpe ,  Adi Habusha

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/455

Abstract: Disclosed herein are techniques for balancing and reducing the number of write operations performed to each physical memory page of a storage-class memory. In one embodiment, a method includes tracking a count of write operations performed to each physical memory page or subpage of the storage-class memory using a memory management unit, a memory controller, a hypervisor, or an operating system, and selectively allocating physical memory pages of the storage-class memory with the least counts of write operations to a virtual machine or an operating system process using a ranking of the physical memory pages of the storage-class memory determined based at least partially on the count of write operations performed to each physical memory page or subpage of the storage-class memory.

公开(公告)号：US10884790B1

公开(公告)日：2021-01-05

申请号：US15969650

申请日：2018-05-02

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/1009 ,  G06F12/1081 ,  G06F3/06 ,  G06F12/1027

Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. A hypervisor may clear the dirty pages and schedule the copy operations of the modified pages in a processing engine for copying to a target device. In one embodiment, before initiating the copy operation, the processing engine may check if the page has been modified again and omit the copy operation if the page has been modified again.

公开(公告)号：US10691576B1

公开(公告)日：2020-06-23

申请号：US15716319

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Yaniv Shapira ,  Gil Stoler ,  Adi Habusha

IPC: G06F11/36 ,  G01R31/317 ,  G06F11/263 ,  G01R31/3177 ,  G06F11/22 ,  G06F11/267

Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

公开(公告)号：US10437748B1

公开(公告)日：2019-10-08

申请号：US14983291

申请日：2015-12-29

Applicant: Amazon Technologies, Inc.

Inventor： Leah Shalev ,  Adi Habusha ,  Georgy Machulsky ,  Nafea Bshara ,  Eric Jason Brandwine

IPC: G06F13/40 ,  G06F13/16

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

公开(公告)号：US10261935B1

公开(公告)日：2019-04-16

申请号：US15280455

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Leah Shalev ,  Nafea Bshara ,  Said Bshara

IPC: G06F13/12 ,  G06F13/42 ,  G06F9/455 ,  H04W84/12 ,  H04L29/06

Abstract: Provided are systems and methods for detecting excessive use of a peripheral device by host processes. In various implementations, a peripheral device can include an integrated circuit that includes a traffic counter. The traffic counter can increment based on events received by the peripheral device. The peripheral device can further include an integrated circuit device configured to associate the traffic counter with a process executing on a host device. The integrated circuit device can further initialize a rate counter for the process. When the rate counter reaches a pre-determined time limit, the integrated circuit device can determine that the process is exceeding a usage limit. The integrated circuit device can further read a value from the traffic counter to verify usage of the peripheral device by the process.

公开(公告)号：US10241951B1

公开(公告)日：2019-03-26

申请号：US15796630

申请日：2017-10-27

Applicant: Amazon Technologies, Inc.

Inventor： Hani Ayoub ,  Adi Habusha ,  Ronen Shitrit

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

公开(公告)号：US10191865B1

公开(公告)日：2019-01-29

申请号：US15099546

申请日：2016-04-14

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Netanel Israel Belgazal ,  Said Bshara ,  Nafea Bshara ,  Adi Habusha

IPC: G06F13/24 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F9/455

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.