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公开(公告)号：US11175917B1
公开(公告)日：2021-11-16
申请号：US17018875
申请日：2020-09-11
Applicant: Apple Inc.
Inventor： Mridul Agarwal , Kulin N. Kothari , Nikhil Gupta
Abstract: In an embodiment, a processor comprises a reservation station that issues a first load operation for execution, a store queue, and a replayed load buffer coupled in parallel with the reservation station. During execution of the first load operation, the store queue detects that the first load operation hits on a first store operation in the store queue that lacks store data and causes a replay of the first load operation. The replayed load buffer captures an identifier of the first load operation and the first store operation based on the replay of the first load operation, wherein the replayed load buffer monitors the reservation station for issuance of a first store data operation corresponding to the first store operation and issues the first load operation for reexecution based on the issuance of the first store data operation.
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公开(公告)号：US20210072997A1
公开(公告)日：2021-03-11
申请号：US16562675
申请日：2019-09-06
Applicant: Apple Inc.
Inventor： Kulin N. Kothari , Mridul Agarwal
Abstract: A processor includes a load/store unit that includes one or more load pipelines and one or more store pipelines. Load operations may be issued into the load pipelines out of order with respect to older store operations. If a load operation is executed out or order with an older store operation that writes one or more bytes read by the load operation, and if the store operation is issued shortly after the load operation, such that the load operation is still in the load pipeline when the store operation is issued, some cases of flushing may be converted to replays by detecting the ordering violation while the load operation is still in the load pipeline.
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公开(公告)号：US20210049015A1
公开(公告)日：2021-02-18
申请号：US16539684
申请日：2019-08-13
Applicant: Apple Inc.
Inventor： Yuan C. Chou , Viney Gautam , Wei-Han Lien , Kulin N. Kothari , Mridul Agarwal
IPC: G06F9/345 , G06F9/38 , G06F9/30 , G06F9/50 , G06F12/0802
Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.
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公开(公告)号：US12007920B2
公开(公告)日：2024-06-11
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11914511B2
公开(公告)日：2024-02-27
申请号：US16907740
申请日：2020-06-22
Applicant: Apple Inc.
Inventor： Francesco Spadini , Gideon Levinsky , Mridul Agarwal
IPC: G06F12/0804 , G06F9/30 , G06F9/38
CPC classification number: G06F12/0804 , G06F9/30043 , G06F9/3826 , G06F9/3834 , G06F2212/601
Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.
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Patent Agency Ranking
公开(公告)号：US20230333851A1
公开(公告)日：2023-10-19
申请号：US18336704
申请日：2023-06-16
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F12/0238 , G06F12/0875 , G06F9/30047 , G06F9/3834 , G06F9/30101
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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公开(公告)号：US20230251985A1
公开(公告)日：2023-08-10
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11720360B2
公开(公告)日：2023-08-08
申请号：US17469504
申请日：2021-09-08
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/3834 , G06F12/0238 , G06F12/0875
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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公开(公告)号：US11630789B2
公开(公告)日：2023-04-18
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20210397555A1
公开(公告)日：2021-12-23
申请号：US16907740
申请日：2020-06-22
Applicant: Apple Inc.
Inventor： Francesco Spadini , Gideon Levinsky , Mridul Agarwal
IPC: G06F12/0804 , G06F9/30
Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.
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