公开(公告)号：US09679891B2

公开(公告)日：2017-06-13

申请号：US14220293

申请日：2014-03-20

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Xiaofeng Fan ,  Geertjan Joordens

IPC: H01L27/02 ,  H02H3/20 ,  H02H3/22 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H02H3/20 ,  H02H3/22 ,  H02H9/046

Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

公开(公告)号：US20150380397A1

公开(公告)日：2015-12-31

申请号：US14501773

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Xiaofeng Fan

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0255

Abstract: Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit.

Abstract translation: 公开了ESD保护电路的各种实施例及其操作方法。 在一个实施例中，一个或多个驱动器电路由被配置为响应于ESD事件激活和放电电流的第一ESD保护电路来保护。 驱动器电路可以包括每个耦合以驱动输出节点的上拉晶体管和下拉晶体管。 第二ESD保护电路可以与驱动器电路中的上拉晶体管相关联并且专用于上拉晶体管。

公开(公告)号：US20150255142A1

公开(公告)日：2015-09-10

申请号：US14196793

申请日：2014-03-04

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: G11C11/4074 ,  H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L27/108 ,  H01L49/02

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C7/02 ,  G11C14/0018 ,  G11C29/021 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.

Abstract translation: 一个或多个集成电路，包括在DRAM制造工艺中制造的至少一个集成电路。 DRAM制造的集成电路中的电容器可以用于集成电路的逻辑部件的去耦，并且可以用于细粒度片上PMU。 可以使用嵌入式DRAM存储器来代替SRAM存储器，具有增加的密度和减少的泄漏。 使用集成电路可以实现更紧凑的系统。

公开(公告)号：US20250062236A1

公开(公告)日：2025-02-20

申请号：US18818493

申请日：2024-08-28

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/532 ,  H01L25/065

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：US20250029921A1

公开(公告)日：2025-01-23

申请号：US18792451

申请日：2024-08-01

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US12159835B2

公开(公告)日：2024-12-03

申请号：US18339102

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20240387390A1

公开(公告)日：2024-11-21

申请号：US18671478

申请日：2024-05-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US12021035B2

公开(公告)日：2024-06-25

申请号：US17931343

申请日：2022-09-12

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L22/32 ,  H01L23/488 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/58 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L22/34 ,  H01L24/06

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20240105704A1

公开(公告)日：2024-03-28

申请号：US18458918

申请日：2023-08-30

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  G02B6/43 ,  H01L23/00

CPC classification number: H01L25/18 ,  G02B6/43 ,  H01L24/08 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/08145 ,  H01L2224/08225

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20240105626A1

公开(公告)日：2024-03-28

申请号：US18296587

申请日：2023-04-06

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  SivaChandra Jangam ,  Zhitao Cao

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49894 ,  H01L23/5383 ,  H01L28/40

Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.