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32 条记录 (耗时 0.02 秒)

    Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory device
    22.
    发明申请
    Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory device 审中-公开
    具有重定时电路的存储器系统以及在存储器控制器和存储器件之间交换数据和定时信号的方法

    公开(公告)号：US20070288716A1

    公开(公告)日：2007-12-13

    申请号：US11449855

    申请日：2006-06-09

    申请人： Edoardo Prete ,  Anthony Sanders ,  Maurizio Skerlj ,  Ulrich Lange

    发明人： Edoardo Prete ,  Anthony Sanders ,  Maurizio Skerlj ,  Ulrich Lange

    IPC分类号： G06F13/00

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/222

    摘要： The present invention refers to a memory system with a controller and a memory device with a communication channel with a data path and a timing path coupling the controller with the memory device. The communication channel has different propagation times for the data path and the timing path exchanging a information signal and a timing signal between the controller and the memory device. The timing signals are used for determining the value of the information signal, and a retiming circuit that is connected with the communication channel compensates, depending on a compensation signal on an input, the delay between the data path and the timing path for exchanging a information signal and a timing signal between the controller and the memory device.

    摘要翻译： 本发明涉及具有控制器和具有与数据路径的通信信道和将控制器与存储器件耦合的定时路径的存储器件的存储器系统。 通信信道具有不同的传播时间，用于数据路径和定时路径交换信息信号和控制器与存储设备之间的定时信号。 定时信号用于确定信息信号的值，并且与通信信道连接的重定时电路根据输入端的补偿信号补偿数据路径与用于交换信息的定时路径之间的延迟 信号和控制器与存储器件之间的定时信号。

    Compensation circuit for driver circuits
    23.
    发明授权
    Compensation circuit for driver circuits 有权
    驱动电路补偿电路

    公开(公告)号：US06486699B1

    公开(公告)日：2002-11-26

    申请号：US09936068

    申请日：2001-12-19

    申请人： Dirk Friebe ,  Anthony Sanders

    发明人： Dirk Friebe ,  Anthony Sanders

    IPC分类号： H03K1716

    CPC分类号： H03K19/00384

    摘要： The invention relates to a compensation circuit for driver circuits having a current reference source which generates at least one reference signal which is modulated with respect to an input signal, having a current-comparison source which generates at least one comparison signal which is modulated with respect to the input signal, the modulated comparison signals having an inverse characteristic to that of the modulated reference signals in respect of the parameters to be modulated, having a comparison unit to which the modulated reference signals and the modulated comparison signals are fed and which generates from a comparison of these modulated modulating signals at least one digital output signal which can be fed to driver circuits connected downstream.

    摘要翻译： 本发明涉及一种用于具有电流参考源的驱动器电路的补偿电路，其产生相对于输入信号被调制的至少一个参考信号，该参考信号具有产生至少一个比较信号的电流比较源，所述比较信号相对于 对于输入信号，调制的比较信号相对于要调制的参数具有与调制的参考信号相反的特性，具有调制的参考信号和调制的比较信号被馈送到的比较单元， 这些调制调制信号的比较可以将至少一个数字输出信号馈送到连接在下游的驱动电路。

    Fast Phase Alignment for Clock and Data Recovery
    25.
    发明申请
    Fast Phase Alignment for Clock and Data Recovery 失效
    快速相位对准时钟和数据恢复

    公开(公告)号：US20100322367A1

    公开(公告)日：2010-12-23

    申请号：US12490185

    申请日：2009-06-23

    申请人： Holger Wenske ,  Anthony Sanders ,  Christian Kreuzer

    发明人： Holger Wenske ,  Anthony Sanders ,  Christian Kreuzer

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091

    摘要： Disclosed herein are systems and methods for fast phase alignment and clock and data recovery. Systems and methods may include a fast phase alignment component configured to generate a selected phase signal based on a characteristic of an incoming signal. A clock and data recovery component may also be configured to receive the selected phase signal and perform a clock and data recovery function on the incoming signal using the selected phase signal.

    摘要翻译： 这里公开了用于快速相位对准和时钟和数据恢复的系统和方法。 系统和方法可以包括快速相位对准部件，其被配置为基于输入信号的特性产生所选择的相位信号。 时钟和数据恢复组件还可以被配置为接收所选择的相位信号，并且使用所选择的相位信号对输入信号执行时钟和数据恢复功能。

    Clock signal extraction device and method for extracting a clock signal from data signal
    27.
    发明授权
    Clock signal extraction device and method for extracting a clock signal from data signal 有权
    时钟信号提取装置和从数据信号提取时钟信号的方法

    公开(公告)号：US07532695B2

    公开(公告)日：2009-05-12

    申请号：US10530852

    申请日：2002-10-10

    申请人： Anthony Sanders ,  Edoardo Prete

    发明人： Anthony Sanders ,  Edoardo Prete

    IPC分类号： H03D3/24

    CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033

    摘要： A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal. The device also includes a clock generator for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. A method for extracting a clock signal from a periodic data signal is related to the device.

    摘要翻译： 一种用于从周期性数据信号中提取时钟信号的时钟信号提取装置包括相位检测器，用于检测所述数据信号的上升沿与上升沿时钟信号之间的第一相位差，并且用于检测所述数据信号的下降沿之间的第二相位差 数据信号和下降沿时钟信号。 该装置还包括时钟发生器，用于产生所述上升沿时钟信号，使得所述第一相位差被最小化，用于产生所述下降沿时钟信号，使得所述第二相位差最小化，并且用于根据所述第一相位差产生所述时钟信号 相位差和所述第二相位差。 从周期性数据信号中提取时钟信号的方法与该装置有关。

    Clock and data recovery circuit including first and second stages
    29.
    发明申请
    Clock and data recovery circuit including first and second stages 审中-公开
    时钟和数据恢复电路包括第一和第二阶段

    公开(公告)号：US20070183552A1

    公开(公告)日：2007-08-09

    申请号：US11346903

    申请日：2006-02-03

    申请人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

    发明人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

    IPC分类号： H03D3/24

    CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0995

    摘要： A clock and data recovery circuit including a first circuit and a second circuit. The first circuit is configured to receive a clock signal and a phase control signal and to lock onto the clock signal and provide a cleaned clock signal. The second circuit is configured to receive a data signal and the cleaned clock signal and to sample the data signal via the cleaned clock signal and provide the phase control signal. The first circuit adjusts the phase of the cleaned clock signal based on the phase control signal.

    摘要翻译： 一种包括第一电路和第二电路的时钟和数据恢复电路。 第一电路被配置为接收时钟信号和相位控制信号，并锁定到时钟信号上并提供清洁的时钟信号。 第二电路被配置为接收数据信号和清除的时钟信号，并且经由清除的时钟信号对数据信号进行采样并提供相位控制信号。 第一个电路基于相位控制信号来调整清除的时钟信号的相位。

    Clock signal extraction device and method for extraction a clock signal from data signal
    30.
    发明申请
    Clock signal extraction device and method for extraction a clock signal from data signal 有权
    时钟信号提取装置和从数据信号中提取时钟信号的方法

    公开(公告)号：US20060023827A1

    公开(公告)日：2006-02-02

    申请号：US10530852

    申请日：2002-10-10

    申请人： Anthony Sanders ,  Edoardo Prete

    发明人： Anthony Sanders ,  Edoardo Prete

    IPC分类号： H03D3/24 ,  H03L7/06

    CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033

    摘要： The invention provides a clock signal extraction device for extracting a clock signal from a periodic data signal, comprising a phase detector (104, 106) for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal; and a clock generator (110, 112) for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. The invention further provides a method for extracting a clock signal from a periodic data signal.

    摘要翻译： 本发明提供了一种用于从周期性数据信号中提取时钟信号的时钟信号提取装置，包括用于检测所述数据信号的上升沿与上升沿时钟信号之间的第一相位差的相位检测器（104,106），并用于检测 所述数据信号的下降沿与下降沿时钟信号之间的第二相位差; 以及时钟发生器（110,112），用于产生所述上升沿时钟信号，使得所述第一相位差最小化，用于产生所述下降沿时钟信号，使得所述第二相位差最小化，并且用于根据 所述第一相位差和所述第二相位差。 本发明还提供了一种从周期性数据信号中提取时钟信号的方法。