公开(公告)号：US06667511B1

公开(公告)日：2003-12-23

申请号：US08993368

申请日：1997-12-18

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

摘要： A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure (346) containing an interpoly dielectric layer (322) for one or more flash memory cells in a core region (305). The method also includes forming a select gate transistor structure (348) having a first gate oxide (322) formed of the interpoly dielectric material and a gate conductor (338) overlying the first gate oxide (322) in the core region (305). A NAND-type flash memory device includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (348) and a periphery region (314, 315) comprising a low voltage transistor (342) and a high voltage transistor (350). The stacked gate flash memory cell structure (346) includes a tunnel oxide layer (308), a poly1 layer (312) overlying the tunnel oxide layer (308), an interpoly dielectric layer (322) formed of an insulating material overlying the poly1 layer (312) and a poly2 layer (338) overlying the interpoly dielectric layer (322). In addition, the select gate transistor structure (348) includes a gate insulator (322) formed of the insulating material and a poly2 layer (338) overlying the gate insulator (322).

摘要翻译： 一种形成NAND型闪速存储器件的方法，包括形成堆叠的栅极闪存结构（346），该堆叠栅极闪存结构（346）包含用于核心区域（305）中的一个或多个闪速存储器单元的互聚电介质层（322）。 该方法还包括形成选择栅极晶体管结构（348），该选择栅极晶体管结构（348）具有由多晶硅间介电材料形成的第一栅极氧化物（322）和覆盖芯区域（305）中的第一栅极氧化物（322）的栅极导体（338）。 NAND型闪速存储器件包括包括堆叠栅极快闪存储器单元结构（346）和选择栅极晶体管（348）的核心区域（305）和包括低压晶体管（342）的外围区域（314,315） 和高压晶体管（350）。 层叠栅极快闪存储单元结构（346）包括隧道氧化物层（308），覆盖隧道氧化物层（308）的多晶硅层（312），由绝缘材料形成的多晶硅绝缘层（322） （312）和覆盖在多晶硅间介电层（322）上的多晶硅层（338）。 此外，选择栅极晶体管结构（348）包括由绝缘材料形成的栅极绝缘体（322）和覆盖栅极绝缘体（322）的多晶硅层（338）。

公开(公告)号：US06448609B1

公开(公告)日：2002-09-10

申请号：US09429244

申请日：1999-10-28

申请人： Masaaki Higashitani ,  Hao Fang

发明人： Masaaki Higashitani ,  Hao Fang

IPC分类号： H01L29792

CPC分类号： H01L22/34

摘要： A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

摘要翻译： 一种使用多晶硅纵梁监测器在存储器阵列上检测多晶硅桁条存在的系统和方法。 多晶硅纵梁监视器包括连续的2层多晶硅，跨越有源区形成第一行和第二行，并覆盖第一行和第二行之间的有源区。 多晶硅纵梁监视器还包括在第一行下方延伸的连续的1层多晶硅，其中第一层也覆盖第一行和第二行之间的有效区域，并且覆盖第二行下方的有效区域 。

公开(公告)号：US06448594B1

公开(公告)日：2002-09-10

申请号：US09539307

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

发明人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

IPC分类号： H01L2976

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  Y10S257/90

摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 在本发明的第一方面中，公开了一种半导体器件。 半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。 在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。 用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物 栅堆叠，其中所述至少一个氧化物间隔物是三角形的。 通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。 这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。 通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。 因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06417990B1

公开(公告)日：2002-07-09

申请号：US09639700

申请日：2000-08-16

申请人： Yuming Zhou ,  Hao Fang ,  Nurul Amin

发明人： Yuming Zhou ,  Hao Fang ,  Nurul Amin

IPC分类号： G11B5147

CPC分类号： G11B5/313 ,  G11B5/3146 ,  G11B5/3967

摘要： A magnetic transducing head having an air bearing surface has a bottom shield, a shared pole, a read element, a substantially planar composite top pole; and a conductive coil. The read element is positioned between the bottom shield and the shared pole. The top pole is formed of high magnetic moment pole tip portion and a high resistivity yoke portion. The pole tip portion of the top pole is substantially coplanar with the yoke portion of the top pole. The pole tip portion of the top pole is separated from the shared pole at the air bearing surface by a write gap, while the yoke portion of the top pole is in contact with the shared pole opposite the air bearing surface. At least a portion of the conductive coil is positioned between the shared pole and the top pole.

摘要翻译： 具有空气轴承表面的磁转换头具有底部屏蔽，共享极，读取元件，基本上平面的复合顶部极; 和导电线圈。 读取元件位于底部屏蔽和共享极之间。 顶极由高磁矩极尖部分和高电阻率磁轭部分形成。 顶极的极尖部分与顶极的轭部基本共面。 顶极的极尖部分通过写入间隙与空气轴承表面的共享极分离，而顶极的轭部与与空气支承表面相对的共享极接触。 导电线圈的至少一部分位于共享极和顶极之间。

公开(公告)号：US06410949B1

公开(公告)日：2002-06-25

申请号：US09774327

申请日：2001-01-31

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218242

摘要： The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.

公开(公告)号：US06346737B1

公开(公告)日：2002-02-12

申请号：US09109755

申请日：1998-07-02

申请人： Masaaki Higashitani ,  Hao Fang

发明人： Masaaki Higashitani ,  Hao Fang

IPC分类号： H01L2900

CPC分类号： H01L21/76235 ,  H01L21/76202 ,  H01L21/76224

摘要： A process which includes forming trench structures (28) in a substrate (12) as part of both the STI isolation structure and the LOCOS/STI isolation structure. Thereafter, a field oxide (34a) is formed which simultaneously forms a portion of the STI isolation structure and a portion of the LOCOS/STI isolation structure. Consequently, three different isolation structures may be formed without requiring a substantial increase in the complexity or number of processing steps.

摘要翻译： 包括在衬底（12）中形成作为STI隔离结构和LOCOS / STI隔离结构两者的一部分的沟槽结构（28）的工艺。 此后，形成场同时形成STI隔离结构的一部分和LOCOS / STI隔离结构的一部分的场氧化物（34a）。 因此，可以形成三个不同的隔离结构，而不需要大大增加处理步骤的复杂性或数量。

公开(公告)号：US06175522B1

公开(公告)日：2001-01-16

申请号：US09408846

申请日：1999-09-30

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： The source end of a NAND string in a scalable, lower voltage flash memory device is biased during a memory read operation to prevent problems associated with punchthrough. Due to the biasing, the channel length of the floating gate transistors in the flash memory device can be shortened, and the pass voltage employed during the memory read operation can be lowered.

摘要翻译： 可扩展的低电压闪存器件中的NAND串的源极在存储器读取操作期间被偏置以防止与穿透相关的问题。 由于偏置，可以缩短闪存器件中的浮置栅极晶体管的沟道长度，并且可以降低在存储器读取操作期间采用的通过电压。

公开(公告)号：US6159795A

公开(公告)日：2000-12-12

申请号：US109664

申请日：1998-07-02

申请人： Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian

发明人： Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/976

摘要： An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.

摘要翻译： 执行中间植入步骤以优化浮动型存储器集成电路的周边部分中的晶体管的性能。 在相应的浮动栅型存储器件中形成浮置栅极的多晶硅层（Poly 1）防止优化注入穿透到形成浮栅存储器件的芯区域中。 这允许在不需要附加掩模的情况下执行优化植入，从而降低成本和生产时间。

公开(公告)号：US6143608A

公开(公告)日：2000-11-07

申请号：US283308

申请日：1999-03-31

申请人： Yue-Song He ,  Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian ,  Bill Cox ,  Kent Chang ,  Kelwin Ko ,  Maria Chow-Chan

发明人： Yue-Song He ,  Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian ,  Bill Cox ,  Kent Chang ,  Kelwin Ko ,  Maria Chow-Chan

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.

摘要翻译： 本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。 所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。 通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。 本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。 用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

公开(公告)号：US6133746A

公开(公告)日：2000-10-17

申请号：US163414

申请日：1998-09-30

申请人： Peng Fang ,  Hao Fang

发明人： Peng Fang ,  Hao Fang

IPC分类号： G01N27/92 ,  H01L23/544 ,  G01R31/12 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01N27/92

摘要： A method for determining a reliable gate oxide thickness for a transistor involves subjecting test transistors to an alternating current (AC) voltage until the test transistors break down. The breakdown times of the test transistors are measured and correlated with the corresponding gate oxide thickness of the test transistor to form a reliability model of the transistor. The reliable gate oxide thickness is determined by extrapolating the reliability model out to a predetermined period of time for which reliability is desired, for example, ten years.

摘要翻译： 用于确定晶体管的可靠栅极氧化物厚度的方法包括使测试晶体管经受交流（AC）电压，直到测试晶体管分解为止。 测量测试晶体管的击穿时间并与测试晶体管的相应栅极氧化物厚度相关联，以形成晶体管的可靠性模型。 可靠的栅极氧化物厚度通过将可靠性模型推断到需要可靠性的预定时间段（例如十年）来确定。