公开(公告)号：US06249030B1

公开(公告)日：2001-06-19

申请号：US08586365

申请日：1996-01-16

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L2976

CPC分类号： H01L21/8249

摘要： The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

摘要翻译： 本发明涉及一种BI-CMOS工艺，其中在公共衬底上制造场效应晶体管（FET）和双极结晶体管（BJT）。 在几个处理步骤中，与BJT结构同时形成FET结构。 例如，在一个步骤中，同时形成用于BJT的用于FET的多晶硅栅电极和多晶硅发射极。 在本发明的另一方面，多晶硅层用于减少否则在植入步骤期间会发生的沟道化。

公开(公告)号：US5963825A

公开(公告)日：1999-10-05

申请号：US935301

申请日：1992-08-26

申请人： Steven S. Lee ,  Gayle W. Miller

发明人： Steven S. Lee ,  Gayle W. Miller

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002

摘要： A fusible link and method for its fabrication. A polysilicon pad is formed on top of an insulating layer and covered with a second insulating layer. A trench is selectively etched into the second insulating layer exposing the top of the polysilicon pad. An fusible aluminum link is then formed over the second insulating layer and trench and conformal therewith. When a programming current is driven through the link, the aluminum melts and is absorbed by the polysilicon pad, thereby preventing the link's growback.

摘要翻译： 一种易熔连接及其制造方法。 多晶硅焊盘形成在绝缘层的顶部并被第二绝缘层覆盖。 选择性地将沟槽蚀刻到暴露多晶硅垫顶部的第二绝缘层中。 然后在第二绝缘层和沟槽上形成可熔铝连接并与其共形。 当通过链路驱动编程电流时，铝熔化并被多晶硅焊盘吸收，从而防止链路的长时间退缩。

公开(公告)号：US5447880A

公开(公告)日：1995-09-05

申请号：US224609

申请日：1994-04-05

申请人： Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

发明人： Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

IPC分类号： H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.

摘要翻译： 一种形成非晶硅可编程元件的方法，其需要小于约一平方微米的面积。 该方法包括以下步骤：形成底部导体，在底部导体上沉积层间电介质，在层间电介质中形成通孔，在通孔内沉积底部导体上方的反熔丝层，以及化学气相沉积导电塞 反熔丝层和通孔内。 该方法可以另外包括化学气相沉积在导电插塞上方的顶部导体的步骤。

公开(公告)号：US4910165A

公开(公告)日：1990-03-20

申请号：US267899

申请日：1988-11-04

申请人： Steven S. Lee ,  Dim-Lee Kwong

发明人： Steven S. Lee ,  Dim-Lee Kwong

IPC分类号： C30B25/20 ,  H01L21/205 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/7627 ,  Y10S148/026 ,  Y10S148/117 ,  Y10S148/152

摘要： A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate. Planarization of the structure and exposure of the epitaxial surfaces provides electrically isolated islands of monocrystalline silicon for bipolar and field effect device fabrication. A CMOS implementation of the epitaxial islands is readily undertaken by selective counterdoping in the presence of a mask.

摘要翻译： 绝缘体上硅制造工艺及结构。 制造工艺包括可再现的顺序，其中在掩模存在下各向异性地蚀刻氧化物覆盖的衬底以形成延伸到衬底中的沟槽。 外延硅在沟槽区域选择性地生长在第一材料掺杂和随后的轻掺杂层中。 物质掺杂层在由衬底的表面限定的平面之上延伸。 在选择性去除氧化物之后，物理掺杂的外延层首先在其侧壁暴露于阳极氧化，然后暴露于氧化环境。 将物质掺杂的外延层首先连续地转换成多孔硅，然后将二氧化硅介质隔离，使轻掺杂的外延层与衬底隔离。 外延表面的结构和曝光的平面化提供用于双极和场效应器件制造的电绝缘的单晶硅孤岛。 在存在掩模的情况下，通过选择性反掺杂容易地进行外延岛的CMOS实现。

公开(公告)号：US06593178B1

公开(公告)日：2003-07-15

申请号：US08866968

申请日：1997-06-02

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L218238

CPC分类号： H01L21/8249

摘要： The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

公开(公告)号：US5734119A

公开(公告)日：1998-03-31

申请号：US769400

申请日：1996-12-19

申请人： Gordon Scott France ,  Steven S. Lee

发明人： Gordon Scott France ,  Steven S. Lee

IPC分类号： G10H1/00 ,  G10H1/06 ,  G10H7/00

CPC分类号： G10H1/0066 ,  G10H1/0058 ,  G10H1/0075 ,  G10H2240/305

摘要： An Internet high fidelity audio transmission and compression protocol including a system for representing synthesized music in a relatively small file as compared to digital recording. The protocol includes a method for streaming the transmission of a music data file from a Server-Composer computer such that the music can begin being played back as soon as the file begins to arrive at a Client-Player computer. The system includes a graduated resolution improvement feature which allows the music to be recreated exactly as originally composed as the necessary wavetable data is downloading in the background and the music continues to play in the foreground.

摘要翻译： 一种互联网高保真音频传输和压缩协议，包括与数字记录相比在相对小的文件中表示合成音乐的系统。 该协议包括用于从服务器 - 作曲家计算机流式传输音乐数据文件的方法，使得一旦文件开始到达客户端 - 播放器计算机就可开始播放音乐。 该系统包括分级分辨率改进功能，其允许按照最初的组合重新创建音乐，因为必要的波表数据正在背景中下载并且音乐在前景中继续播放。

公开(公告)号：US5543361A

公开(公告)日：1996-08-06

申请号：US351843

申请日：1994-12-08

申请人： Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

发明人： Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/76895 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/147

摘要： A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

公开(公告)号：US5516718A

公开(公告)日：1996-05-14

申请号：US331235

申请日：1994-10-25

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/8249 ,  Y10S148/009 ,  Y10S148/124

摘要： The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

摘要翻译： 本发明涉及一种BI-CMOS工艺，其中在公共衬底上制造场效应晶体管（FET）和双极结晶体管（BJT）。 在几个处理步骤中，与BJT结构同时形成FET结构。 例如，在一个步骤中，同时形成用于BJT的用于FET的多晶硅栅电极和多晶硅发射极。 在本发明的另一方面，多晶硅层用于减少否则在植入步骤期间会发生的沟道化。

公开(公告)号：US5248350A

公开(公告)日：1993-09-28

申请号：US622107

申请日：1990-11-30

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76221

摘要： A process for forming field oxide regions between active regions in a semiconductor substrate. Pad oxide, polysilicon and first silicon nitride layers are successively formed over substrate active regions. The first nitride layer, polysilicon layer, pad oxide layer and a portion of the substrate are then selectively etched to define field oxide regions with substantially vertical sidewalls. A second silicon nitride is provided on the substantially vertical sidewalls, and field oxide is grown in the field oxide regions. The first silicon nitride, polysilicon and pad oxide layers are then removed. The presence of the polysilicon layer prevents the formation of a sharp corner between the field oxide and active regions if an overetch occurs during the removal of the pad oxide layer.

公开(公告)号：US5200686A

公开(公告)日：1993-04-06

申请号：US774435

申请日：1991-10-10

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H02J7/00

CPC分类号： H02J7/0091 ,  H02J7/0006

摘要： Battery type is determined by measuring effective resistance of a thermistor/resistor network (205, 206, and 207) and one or more of a plurality of current sources (303-305) is enabled to provide the appropriate charging current. Measurement of necessary charging parameters and provision of appropriate charging current are accomplished through an interface to the battery pack undergoing charge that comprises only three connections (313-315).

摘要翻译： 电池类型通过测量热敏电阻/电阻网络（205,206和207）的有效电阻来确定，并且多个电流源（303-305）中的一个或多个能够提供适当的充电电流。 必要的充电参数的测量和适当的充电电流的提供是通过一个接口连接电池组，该电池组正在进行电荷，仅包含三个连接（313-315）。