公开(公告)号：US4910165A

公开(公告)日：1990-03-20

申请号：US267899

申请日：1988-11-04

申请人： Steven S. Lee ,  Dim-Lee Kwong

发明人： Steven S. Lee ,  Dim-Lee Kwong

IPC分类号： C30B25/20 ,  H01L21/205 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/7627 ,  Y10S148/026 ,  Y10S148/117 ,  Y10S148/152

摘要： A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate. Planarization of the structure and exposure of the epitaxial surfaces provides electrically isolated islands of monocrystalline silicon for bipolar and field effect device fabrication. A CMOS implementation of the epitaxial islands is readily undertaken by selective counterdoping in the presence of a mask.

摘要翻译： 绝缘体上硅制造工艺及结构。 制造工艺包括可再现的顺序，其中在掩模存在下各向异性地蚀刻氧化物覆盖的衬底以形成延伸到衬底中的沟槽。 外延硅在沟槽区域选择性地生长在第一材料掺杂和随后的轻掺杂层中。 物质掺杂层在由衬底的表面限定的平面之上延伸。 在选择性去除氧化物之后，物理掺杂的外延层首先在其侧壁暴露于阳极氧化，然后暴露于氧化环境。 将物质掺杂的外延层首先连续地转换成多孔硅，然后将二氧化硅介质隔离，使轻掺杂的外延层与衬底隔离。 外延表面的结构和曝光的平面化提供用于双极和场效应器件制造的电绝缘的单晶硅孤岛。 在存在掩模的情况下，通过选择性反掺杂容易地进行外延岛的CMOS实现。

公开(公告)号：US06943413B2

公开(公告)日：2005-09-13

申请号：US10428592

申请日：2003-05-01

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L21/8249 ,  H01L29/76

CPC分类号： H01L21/8249

摘要： The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

摘要翻译： 本发明涉及一种BI-CMOS工艺，其中在公共衬底上制造场效应晶体管（FET）和双极结晶体管（BJT）。 在几个处理步骤中，与BJT结构同时形成FET结构。 例如，在一个步骤中，同时形成用于BJT的用于FET的多晶硅栅电极和多晶硅发射极。 在本发明的另一方面，多晶硅层用于减少否则在植入步骤期间会发生的沟道化。

公开(公告)号：US5904535A

公开(公告)日：1999-05-18

申请号：US748969

申请日：1996-11-13

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L21/8249 ,  H01L21/84 ,  H01L27/12 ,  H01L21/331

CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/1203

摘要： A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

摘要翻译： 一种用于在绝缘体上硅衬底上制造双极晶体管的工艺，其包括将双极晶体管区域蚀刻到衬底中，其中双极晶体管区域具有基本垂直的侧壁和底部，并且在双极晶体管的底部形成掩埋集电极 区。 多晶硅侧壁形成在双极晶体管区域中与垂直侧壁相邻，其中多晶硅侧壁连接到埋地集电器。 多晶硅侧壁被氧化以形成氧化多晶硅层。 在氧化的多晶硅侧壁上形成氧化物侧壁，并且形成外延硅以填充双极晶体管区域。 在外延阻挡层内为双极晶体管形成基极和发射极。

公开(公告)号：US5672905A

公开(公告)日：1997-09-30

申请号：US935306

申请日：1992-08-26

申请人： Steven S. Lee ,  Gayle W. Miller

发明人： Steven S. Lee ,  Gayle W. Miller

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L2924/0002

摘要： A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

摘要翻译： 半导体熔丝及其制造方法设置有绝缘层，并形成有沟槽。 然后在绝缘层和沟槽之间形成可熔连接并与其保持共形。 连接件在沟槽的侧壁和底面的交点处具有最小厚度和宽度的断裂区域。

公开(公告)号：US5581861A

公开(公告)日：1996-12-10

申请号：US460485

申请日：1995-06-02

申请人： Steven S. Lee ,  Gayle W. Miller

发明人： Steven S. Lee ,  Gayle W. Miller

IPC分类号： B41J2/045 ,  B41J2/055 ,  B41J2/16 ,  H01L41/22

CPC分类号： B41J2/1629 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/1634 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2002/14387 ,  Y10T29/42 ,  Y10T29/49401

摘要： An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.

摘要翻译： 喷墨打印头包括形成在第一基板上的墨驱动单元和形成在第二基板上的墨存储单元。 墨驱动单元包括形成在基板一侧的薄膜压电换能器。 储存器单元包括用于形成油墨储存器的衬底中的蚀刻腔，该空腔在基体中具有延伸穿过衬底的孔以形成油墨喷嘴。 墨水驱动器和墨水储存器单元与墨水储存器内的压电换能器结合在一起。 激活传感器通过墨水喷嘴从储存器排出墨水。

公开(公告)号：US5332957A

公开(公告)日：1994-07-26

申请号：US937569

申请日：1992-08-31

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H02J7/00 ,  H02J1/00

CPC分类号： H02J7/0006

摘要： A battery module (200) includes a preselected one (105) of a plurality of discrete electrodes (102-105) that is either electrically uncoupled, or is coupled in a fashion that is redundant with respect to one of the other electrodes (102-104). A battery module constructed in this fashion is compatible with both a microprocessor controlled rapid charger (400) and a trickle charger (500) constructed from simple discrete circuitry.

摘要翻译： 电池模块（200）包括多个分立电极（102-105）中的预选的一个（105），所述多个分立电极（102-105）电解脱耦合，或者以相对于其它电极（102- 104）。 以这种方式构造的电池模块与由简单的离散电路构成的微处理器控制的快速充电器（400）和涓流充电器（500）兼容。

公开(公告)号：US06610822B2

公开(公告)日：2003-08-26

申请号：US09920497

申请日：2001-08-01

申请人： Martin A. Chandler ,  Kent E. Goklen ,  Steven S. Lee ,  David J. Roush

发明人： Martin A. Chandler ,  Kent E. Goklen ,  Steven S. Lee ,  David J. Roush

IPC分类号： C07K114

CPC分类号： C07K7/56

摘要： There is disclosed a process for purifying a natural product using a two-phase, multi-solvent system followed by vacuum concentration and back extraction. The method allows for the removal of impurities by controlling the polarity balance of a two-phase system by manipulating the proportions of the four solvents and subsequently the relative distribution of the product versus the impurities.

公开(公告)号：US06232649B1

公开(公告)日：2001-05-15

申请号：US08354574

申请日：1994-12-12

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L27082

CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L29/7317

摘要： A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

摘要翻译： 一种用于在绝缘体上硅衬底上制造双极晶体管的方法，其包括将双极晶体管区域蚀刻到衬底中，其中双极晶体管区域具有基本垂直的侧壁和底部，并且在双极晶体管的底部形成掩埋集电极 区。 多晶硅侧壁形成在双极晶体管区域中与垂直侧壁相邻，其中多晶硅侧壁连接到埋地集电器。 多晶硅侧壁被氧化以形成氧化多晶硅层。 在氧化的多晶硅侧壁上形成氧化物侧壁，并且形成外延硅以填充双极晶体管区域。 在外延阻挡层内为双极晶体管形成基极和发射极。

公开(公告)号：US5728626A

公开(公告)日：1998-03-17

申请号：US553788

申请日：1995-10-23

申请人： Derryl D. J. Allman ,  Steven S. Lee

发明人： Derryl D. J. Allman ,  Steven S. Lee

IPC分类号： H01L21/288 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L29/78 ,  B05D3/02 ,  B05D5/12 ,  H01L21/445

CPC分类号： H01L21/288 ,  H01L21/7684 ,  H01L21/76877

摘要： A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

摘要翻译： 平面化非平面衬底（例如填充通孔和接触孔）的方法将悬浮在液体中的导电材料的悬浮液铺展在衬底上。 悬浮液包括有机金属材料，优选具有聚合的锡或烷氧基铟的颗粒。 施加悬浮液后，通过旋转基材来铺展材料。 载体液体和有机基团通过在升高的温度下烘烤和固化来除去，从而将导电材料沉积在基底上比基底更平坦且具有较大和较小厚度的区域的层中。 相对短暂的蚀刻步骤从较小厚度的区域去除导电材料，留下填充通孔或接触孔的材料。

公开(公告)号：US4986879A

公开(公告)日：1991-01-22

申请号：US436567

申请日：1990-03-19

申请人： Steven S. Lee

发明人： Steven S. Lee

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76205

摘要： An integrated circuit structure and fabrication process for creating field oxide regions having substantially no bird's beak, a relatively planar concluding surface, substantially no stress induced dislocations at the edges of the active regions, and a substantial absence of notches or grooves at the edges of the active silicon, by a selective combination of material dimensions and process operations. In one form of practicing the invention, the process utilizes a relatively thick pad oxide below the masking nitride layer, and a second, very thin, sidewall masking nitride layer. The thin sidewall masking nitride layer does not utilize an underlying pad oxide layer, but may include a thin underlying screening oxide. Upon oxidation, the thin sidewall nitride is concurrently lifted and converted to oxide, the materials and dimension being selected to ensure that when the field oxide level approaches the level of the thick pad oxide layer stresses at the corners of the active silicon region are relieved through various oxide paths and accentuated oxidation effects.

摘要翻译： 一种集成电路结构和制造方法，用于产生基本上没有鸟喙的场氧化物区域，相对平面的结论表面，在有源区域的边缘处基本上没有应力引起的位错，并且在边缘处基本上没有凹口或凹槽 活性硅，通过材料尺寸和工艺操作的选择性组合。 在实施本发明的一种形式中，该方法利用掩模氮化物层下面的较厚的衬垫氧化物和第二非常薄的侧壁掩模氮化物层。 薄侧壁掩模氮化物层不利用下面的衬垫氧化物层，但可以包括薄的底层屏蔽氧化物。 在氧化时，薄侧壁氮化物同时提升并转换成氧化物，选择材料和尺寸以确保当氧化物水平接近厚衬垫氧化物层的水平时，活性硅区域的拐角处的应力通过 各种氧化物路径和强化氧化效应。