公开(公告)号：US07685553B2

公开(公告)日：2010-03-23

申请号：US11733795

申请日：2007-04-11

申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

公开(公告)号：US20080068039A1

公开(公告)日：2008-03-20

申请号：US11945308

申请日：2007-11-27

申请人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim Elfadel ,  Philip Emma ,  Daniel Friedman ,  Ruchir Puri ,  Mark Ritter ,  Jeannine Trewhella ,  Albert Young

发明人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim Elfadel ,  Philip Emma ,  Daniel Friedman ,  Ruchir Puri ,  Mark Ritter ,  Jeannine Trewhella ,  Albert Young

IPC分类号： H03K19/00

CPC分类号： G11C29/006 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/1206

摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

摘要翻译： 一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移 电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

公开(公告)号：US07336100B2

公开(公告)日：2008-02-26

申请号：US11466754

申请日：2006-08-23

申请人： Anthony Correale, Jr. ,  Rajiv V. Joshi ,  David S. Kung ,  Zhigang Pan ,  Ruchir Puri

发明人： Anthony Correale, Jr. ,  Rajiv V. Joshi ,  David S. Kung ,  Zhigang Pan ,  Ruchir Puri

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

公开(公告)号：US20070081410A1

公开(公告)日：2007-04-12

申请号：US11163167

申请日：2005-10-07

申请人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim Elfadel ,  Philip Emma ,  Daniel Friedman ,  Ruchir Puri ,  Mark Ritter ,  Jeannine Trewhella ,  Albert Young

发明人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim Elfadel ,  Philip Emma ,  Daniel Friedman ,  Ruchir Puri ,  Mark Ritter ,  Jeannine Trewhella ,  Albert Young

IPC分类号： G11C8/00

CPC分类号： G11C29/006 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/1206

摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

摘要翻译： 具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路 和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

公开(公告)号：US06601223B1

公开(公告)日：2003-07-29

申请号：US09675634

申请日：2000-09-29

申请人： Ruchir Puri ,  David S. Kung ,  Anthony Drumm

发明人： Ruchir Puri ,  David S. Kung ,  Anthony Drumm

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A system and method are proposed for estimating interconnect delay in an Integrated Circuit (IC). A formula for effective capacitance is derived which considers the effect of slew as well as resistive shielding of capacitance, thus yielding more accurate delays for both the interconnects and the source driver (transistor gate). In the system and method, a resistor-capacitor (RC) tree model is used for iterative calculations of effective capacitance and slew for each RC tree node. The effective capacitance is determined for each node by proceeding outward from the source to the sinks, and the slew for each node is determined, using the effective capacitances just determined, by proceeding inward from the sinks to the source node. Once the source node slew determined at a previous iteration is within a specified threshold of the source node slew in the present iteration, the method stops and stores the present iteration values as the final estimates.

摘要翻译： 提出了一种用于估计集成电路（IC）中的互连延迟的系统和方法。 导出有效电容的公式，其考虑了电压的影响以及电容的电阻屏蔽，从而为互连和源极驱动器（晶体管栅极）产生更精确的延迟。 在系统和方法中，电阻 - 电容（RC）树模型用于每个RC树节点的有效电容和电压的迭代计算。 通过从源极进入接收器，确定每个节点的有效电容，并且使用刚刚确定的有效电容，通过从信宿到源节点向内进行确定每个节点的电压。 一旦在先前迭代中确定的源节点转动在当前迭代中的源节点的指定阈值内，则该方法停止并存储当前迭代值作为最终估计。

公开(公告)号：US5469367A

公开(公告)日：1995-11-21

申请号：US254186

申请日：1994-06-06

申请人： Ruchir Puri ,  Jun Gu

发明人： Ruchir Puri ,  Jun Gu

IPC分类号： G06F17/50

CPC分类号： G06F17/5059

摘要： A machine methodology for designing asynchronous circuits utilizes a modular approach for the synthesis of asynchronous circuits from signal transition graphs, partitions the signal transition graph into a number of simpler and more manageable modules. Each modular graph is then individually solved. The results of the small graphs are then integrated together to provide a solution to the asynchronous circuit design problem as defined by a given asynchronous behavioral specification. A satisfiability solver for Boolean output function utilizing a binary decision diagram is incorporated in one embodiment which is comprised of a structural SAT formula preprocessor and a complete, incremental SAT processor which is specifically designed to find an optimal solution. The preprocessor compresses a large size SAT formula representing a circuit into a number of smaller SAT formulas. Each small size SAT formula is then solved by the BDD SAT processor. The results of these subsolutions are then integrated together to contribute to the solution of the original larger design problem.

摘要翻译： 用于设计异步电路的机器方法利用用于从信号转换图合成异步电路的模块化方法，将信号转换图分解成多个更简单和更易于管理的模块。 然后单独解决每个模块图。 然后将小图的结果集成在一起，以提供由给定的异步行为规范定义的异步电路设计问题的解决方案。 利用二进制决策图的布尔输出功能的可满足求解器被并入一个实施例中，该实施例由结构化SAT公式预处理器和专门设计用于找到最佳解决方案的完整的增量SAT处理器组成。 预处理器将表示电路的大尺寸SAT公式压缩成多个较小的SAT公式。 然后通过BDD SAT处理器解决每个小尺寸的SAT公式。 然后将这些子解决方案的结果集成在一起，以有助于解决原来更大的设计问题。

公开(公告)号：US08495552B1

公开(公告)日：2013-07-23

申请号：US13536601

申请日：2012-06-28

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

摘要翻译： 在集成电路物理合成期间，锁存器和本地时钟缓冲器将自动放置。 在物理布置数据通路之前，基于数据通路的逻辑表示和引脚的固定放置位置为锁存器分配位置。 所计算的锁存位置根据某些预定标准优化数据通路。 本地时钟缓冲器也被预置在一起，锁存器进一步提高了数据通路性能。

公开(公告)号：US08117568B2

公开(公告)日：2012-02-14

申请号：US12237727

申请日：2008-09-25

申请人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

发明人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

公开(公告)号：US20120017186A1

公开(公告)日：2012-01-19

申请号：US12835780

申请日：2010-07-14

申请人： Michael D. Amundson ,  Dorothy Kucar ,  Ruchir Puri ,  Chin Ngai Sze ,  Matthew M. Ziegler

发明人： Michael D. Amundson ,  Dorothy Kucar ,  Ruchir Puri ,  Chin Ngai Sze ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.

摘要翻译： 示例性实施例包括用于修改具有自动指令的电路合成流的方法，该方法包括接收用于电路设计的电路设计输入，接收电路设计输入的定制规范，从电路设计输入合成高电平逻辑，将逻辑放置在 电路设计，精简电路设计，并从电路设计中产生电路描述。

公开(公告)号：US08053819B2

公开(公告)日：2011-11-08

申请号：US12120899

申请日：2008-05-15

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。