公开(公告)号：US20050046019A1

公开(公告)日：2005-03-03

申请号：US10652369

申请日：2003-08-29

申请人： Bruce Whitefield

发明人： Bruce Whitefield

IPC分类号： G01R31/28 ,  H01L23/544 ,  H01L23/34

CPC分类号： H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/303

摘要： A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

公开(公告)号：US06495312B1

公开(公告)日：2002-12-17

申请号：US09879642

申请日：2001-06-12

申请人： Roger Y. B. Young ,  Bruce Whitefield

发明人： Roger Y. B. Young ,  Bruce Whitefield

IPC分类号： G03F722

CPC分类号： G03F7/2028

摘要： A positive photoresist bead is removed from an edge surface of a substrate by exposing the photoresist bead with light from an exposing source along a plurality of non-parallel paths approximately normal to the surface of the photoresist bead. The light may be simultaneously directed by a light guide along the non-parallel paths, or a mount may support the light guide adjacent the bead to move the light guide to various positions to direct the light along the non-parallel paths. Alternatively, plural light sources direct light to the bead along non-parallel paths. In any case, the exposed photoresist bead is then removed with a solvent.

摘要翻译： 通过使光致抗蚀剂珠沿着大致垂直于光致抗蚀剂珠粒表面的多个非平行路径从曝光源曝光来从基板的边缘表面去除正光致抗蚀剂珠粒。 光可以沿着非平行路径同时由光导引导，或者安装件可以支撑邻近珠的光导，以将光导移动到各个位置以引导光沿着非平行路径。 或者，多个光源将光沿着非平行路径引导到珠。 在任何情况下，然后用溶剂除去曝光的光致抗蚀剂珠粒。

公开(公告)号：US5477466A

公开(公告)日：1995-12-19

申请号：US362839

申请日：1994-12-22

申请人： Prabhakar P. Tripathi ,  Bruce Whitefield ,  Chi-Hung Wang

发明人： Prabhakar P. Tripathi ,  Bruce Whitefield ,  Chi-Hung Wang

IPC分类号： H01L21/302 ,  G03F1/08 ,  G06F17/50 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L2924/0002

摘要： A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

公开(公告)号：US07653523B2

公开(公告)日：2010-01-26

申请号：US10736386

申请日：2003-12-15

申请人： Bruce Whitefield ,  David Abercrombie

发明人： Bruce Whitefield ,  David Abercrombie

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： H01L22/20

摘要： An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.

摘要翻译： 本发明的实施例提供一种利用来自许多不同管芯尺寸和产品的数据的方法，从而可以产生具有改善的信噪比和空间分辨率的高度详细的晶片轮廓。 这种方法不仅限于单晶片尺寸，如正常晶片图，而是利用多个晶粒尺寸及其在晶片上的放置变化，以增加关于晶片图案的可用信息。

公开(公告)号：US20080061805A1

公开(公告)日：2008-03-13

申请号：US11937199

申请日：2007-11-08

申请人： Bruce Whitefield

发明人： Bruce Whitefield

IPC分类号： G01R31/305

CPC分类号： H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/303

摘要： A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

摘要翻译： 提供了一种半导体芯片，其包括有源和非活动IP核。 与非活动IP核相关联的金属层上的空间包括电压对比度检查结构。 电压对比检查结构用于提供金属层的改进的平面化并提供改进的检查能力。

公开(公告)号：US20060191634A1

公开(公告)日：2006-08-31

申请号：US11383171

申请日：2006-05-12

申请人： Bruce Whitefield ,  David Abercrombie

发明人： Bruce Whitefield ,  David Abercrombie

IPC分类号： H01L21/306

CPC分类号： H01L21/02087 ,  G03F7/2028 ,  Y10S438/926

摘要： An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

摘要翻译： 一种装置包括边缘曝光单元，用于将晶片的边缘排除区域中的环形区域暴露于具有适于从环形区域中的晶片去除膜的波长的辐射以及耦合到边缘曝光单元的辐射调制器，用于调制 辐射以在环形区域中对膜进行图案化。

公开(公告)号：US20060094246A1

公开(公告)日：2006-05-04

申请号：US10980945

申请日：2004-11-03

申请人： Bruce Whitefield ,  David Abercrombie

发明人： Bruce Whitefield ,  David Abercrombie

IPC分类号： H01L21/469

CPC分类号： H01L21/02087 ,  G03F7/2028 ,  Y10S438/926

摘要： A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

摘要翻译： 一种方法包括以下步骤：（a）提供其上沉积有膜的晶片; （b）将晶片的边缘排除区域中的环形区域暴露于具有适于在环形区域中图案化膜的波长的辐射; 和（c）在暴露环形区域的同时调制辐射，以在环形区域中的膜中形成图案。

公开(公告)号：US20060069659A1

公开(公告)日：2006-03-30

申请号：US10951647

申请日：2004-09-28

申请人： Michael Gatov ,  Deborah Leek ,  Bruce Whitefield

发明人： Michael Gatov ,  Deborah Leek ,  Bruce Whitefield

IPC分类号： G06F17/00

CPC分类号： G06Q10/06 ,  G06Q10/04 ,  G06Q30/0283

摘要： A method of determining a cost effective number of corrective tests to perform on a process experiencing process excursions. A test cost for each corrective test is determined, and a total test cost for each of an incremental number of corrective tests is calculated. An effect of each corrective test on a reduction in the process excursions is determined, as is also the lost revenue for each process excursion. A reduction in the lost revenue for each of the incremental number of corrective tests is calculated, based at least in part on the effect of each corrective test on the reduction in process excursions and the revenue lost for each process excursion. An overall cost for each of the incremental number of corrective tests is calculated, based at least in part on a sum of the total test cost and the reduction in the lost revenue for each of the incremental number of corrective tests. A minimum value of the overall costs is found, and that incremental number of corrective tests that is associated with the minimum value of the overall costs is selected as the cost effective number of corrective tests to perform.

摘要翻译： 确定在经历过程偏差的过程中执行的成本有效数量的校正测试的方法。 确定每个校正测试的测试成本，并计算每个增量数量的校正测试的总测试成本。 确定每个校正测试对减少过程偏差的影响，以及每个过程偏差的收入损失也是如此。 至少部分地基于每次校正测试对减少过程偏差的影响以及每个过程偏差的收入损失，减少每个增量数量的校正测试的损失收入。 至少部分地基于总体测试成本和每个增量修正测试的损失收入减少的总和来计算每个增量数量的校正测试的总体成本。 找到总体成本的最小值，并且选择与整体成本的最小值相关联的校正测试的增量数量作为要执行的校正测试的成本有效数量。

公开(公告)号：US06971944B2

公开(公告)日：2005-12-06

申请号：US10779966

申请日：2004-02-17

申请人： Michael J. Berman ,  Steven E. Reder ,  Bruce Whitefield

发明人： Michael J. Berman ,  Steven E. Reder ,  Bruce Whitefield

IPC分类号： B24B37/04 ,  B24B49/10 ,  B24B1/00

CPC分类号： B24B37/005 ,  B24B49/10

摘要： A method and control system for detecting harmonic oscillation in a chemical mechanical polishing process and reacting thereto, such as by taking steps to at least one of: 1) reduce or eliminate the harmonic oscillation; and 2) counter the noise which is associated with the harmonic oscillation. By reducing or eliminating harmonic oscillation, films with reduced structure strengths including low k dielectric films can be used. By countering the noise, the quality of the work environment is improved.

摘要翻译： 一种用于检测化学机械抛光工艺中的谐波振荡并与其反应的方法和控制系统，例如通过采取以下步骤中的至少一个步骤：1）减少或消除谐波振荡; 和2）对抗与谐波振荡相关的噪声。 通过减少或消除谐波振荡，可以使用包括低k电介质膜的具有降低的结构强度的膜。 通过对付噪声，提高了工作环境的质量。

公开(公告)号：US20050028115A1

公开(公告)日：2005-02-03

申请号：US10628986

申请日：2003-07-28

申请人： Bruce Whitefield ,  Joseph Cowan

发明人： Bruce Whitefield ,  Joseph Cowan

IPC分类号： G01R31/3193 ,  G06F17/50

CPC分类号： G01R31/31935

摘要： A method of mapping logic failures in an integrated circuit die includes steps of: (a) generating a navigation map of test paths for an integrated circuit die; (b) selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths; and (c) calculating a value for each of the cell locations wherein the value is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.

摘要翻译： 映射集成电路管芯中的逻辑故障的方法包括以下步骤：（a）产生用于集成电路管芯的测试路径的导航图; （b）从每个测试路径的导航图中选择网格间距来定义单元格位置的网格图; 以及（c）计算每个单元位置的值，其中该值表示与每个单元位置相交的测试路径的总数与与每个单元位置相交的测试路径的失败数量之间的差异。