公开(公告)号：US20090308578A1

公开(公告)日：2009-12-17

申请号：US12544344

申请日：2009-08-20

申请人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

发明人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC分类号： F28D15/00

CPC分类号： H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

公开(公告)号：US08989532B2

公开(公告)日：2015-03-24

申请号：US13312583

申请日：2011-12-06

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Roger F. Dangel ,  Hubert Harrer ,  Andreas Huber ,  Norbert M. Meier ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper ,  Jonas R. Weiss

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Roger F. Dangel ,  Hubert Harrer ,  Andreas Huber ,  Norbert M. Meier ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper ,  Jonas R. Weiss

IPC分类号： G02B6/12 ,  G02B6/43 ,  G02B6/122

CPC分类号： G02B6/43 ,  G02B6/12002 ,  G02B6/122

摘要： An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

摘要翻译： 集成电路耦合器件包括集成电路封装; 以及连接到集成电路封装的光学数据传输介质，并且包括适于在操作中从集成电路封装件移除热量的可移动冷却剂。

公开(公告)号：US08629554B2

公开(公告)日：2014-01-14

申请号：US12544365

申请日：2009-08-20

申请人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

发明人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC分类号： H01L23/34

CPC分类号： H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

摘要翻译： 一种组件，包括集成电路的芯片，包括集成电路的壳体，并且具有形成在芯片的一侧的上部和形成在芯片的另一侧的下部，用于电连接的多个贯通晶片通孔（TWV） 芯片的集成电路和壳体的集成电路，以及连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US08427833B2

公开(公告)日：2013-04-23

申请号：US12914730

申请日：2010-10-28

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： H05K7/20 ,  H01L25/00

CPC分类号： H01L23/50 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5286 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/09701 ,  Y10T29/49002 ,  Y10T29/49155 ,  H01L2924/014

摘要： A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于传递功率并构成最小热阻的火力发电平面的机构。 该机构包括经由第一组耦合装置耦合到经由第二组耦合装置耦合到处理器层的信令和输入/输出（I / O）层和电力输送层的处理器层。 在该机构中，功率传递层专用于仅传递功率，并且不向机构的元件提供数据通信信号。 在该机构中，电力输送层包括多个导体，多个绝缘材料，一个或多个接地平面以及多个通过层压体的通孔。 在该机制中，信令和输入/输出（I / O）层专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。

公开(公告)号：US08253234B2

公开(公告)日：2012-08-28

申请号：US12914644

申请日：2010-10-28

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1088 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10T29/41 ,  H01L2924/00

摘要： A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于优化三维（3D）超大规模集成（VLSI）器件中的半导体封装的机制。 3D VLSI设备包括经由第一组耦合设备耦合到至少一个信令和输入/输出（I / O）层的处理器层。 3D VLSI设备还包括经由第二组耦合设备耦合到处理器层的功率传递层。 在3D VLSI设备中，功率传递层专用于仅传递功率，并且不向三维VLSI设备的元件提供数据通信信号，并且至少一个信令和输入/输出（I / O）层是 专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。

公开(公告)号：US20120106074A1

公开(公告)日：2012-05-03

申请号：US12914697

申请日：2010-10-28

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： G06F1/20 ,  H05K13/04

CPC分类号： H01L25/18 ,  H01L23/3672 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

摘要： A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于通过散热器进行集成电力输送和分配的机构。 该机构包括经由第一组耦合装置耦合到信令和输入/输出（I / O）层的处理器层，以及经由第二组耦合装置耦合到处理器层的散热器。 在该机构中，散热器包括在一个面上的多个凹槽，其中每个凹槽提供用于功率的路径或用于地面传送到处理器层的路径。 在该机制中，散热器专用于仅传递功率，并且不向机构的元件提供数据通信信号，并且信令和I / O层专用于仅向数据通信信号发送数据通信信号并接收数据通信信号 并且不向处理器层的元件供电。

公开(公告)号：US20090108435A1

公开(公告)日：2009-04-30

申请号：US11933107

申请日：2007-10-31

申请人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

发明人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC分类号： H01L23/50 ,  H01L23/46 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

摘要翻译： 一种组件，包括集成电路的芯片，包括集成电路的壳体，并且具有形成在芯片的一侧的上部和形成在芯片的另一侧的下部，用于电连接的多个贯通晶片通孔（TWV） 芯片的集成电路和壳体的集成电路，以及连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US08476112B2

公开(公告)日：2013-07-02

申请号：US13555451

申请日：2012-07-23

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1088 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10T29/41 ,  H01L2924/00

摘要： A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于优化三维（3D）超大规模集成（VLSI）器件中的半导体封装的机制。 3D VLSI设备包括经由第一组耦合设备耦合到至少一个信令和输入/输出（I / O）层的处理器层。 3D VLSI设备还包括经由第二组耦合设备耦合到处理器层的功率传递层。 在3D VLSI设备中，功率传递层专用于仅传递功率，并且不向三维VLSI设备的元件提供数据通信信号，并且至少一个信令和输入/输出（I / O）层是 专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。

公开(公告)号：US08405998B2

公开(公告)日：2013-03-26

申请号：US12914697

申请日：2010-10-28

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： H05K7/20

CPC分类号： H01L25/18 ,  H01L23/3672 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

摘要： A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于通过散热器进行集成电力输送和分配的机构。 该机构包括经由第一组耦合装置耦合到信令和输入/输出（I / O）层的处理器层，以及经由第二组耦合装置耦合到处理器层的散热器。 在该机构中，散热器包括在一个面上的多个凹槽，其中每个凹槽提供用于功率的路径或用于地面传送到处理器层的路径。 在该机制中，散热器专用于仅传递功率，并且不向机构的元件提供数据通信信号，并且信令和I / O层专用于仅向数据通信信号发送数据通信信号并接收数据通信信号 并且不向处理器层的元件供电。

公开(公告)号：US20120290999A1

公开(公告)日：2012-11-15

申请号：US13555451

申请日：2012-07-23

申请人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

发明人： Harry Barowski ,  Thomas Brunschwiler ,  Hubert Harrer ,  Andreas Huber ,  Bruno Michel ,  Tim Niggemeier ,  Stephan Paredes ,  Jochen Supper

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1088 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10T29/41 ,  H01L2924/00

摘要： A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

摘要翻译： 提供了一种用于优化三维（3D）超大规模集成（VLSI）器件中的半导体封装的机制。 3D VLSI设备包括经由第一组耦合设备耦合到至少一个信令和输入/输出（I / O）层的处理器层。 3D VLSI设备还包括经由第二组耦合设备耦合到处理器层的功率传递层。 在3D VLSI设备中，功率传递层专用于仅传递功率，并且不向三维VLSI设备的元件提供数据通信信号，并且至少一个信令和输入/输出（I / O）层是 专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。