公开(公告)号：US20060151862A1

公开(公告)日：2006-07-13

申请号：US11071389

申请日：2005-03-02

申请人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

发明人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and each of the grooves is connected to an edge of the die pad by at least one of the runners; at least one chip mounted on the other surface of the die pad and electrically connected to the plurality of leads; and an encapsulant for encapsulating the chip, with the runners and grooves being exposed from the encapsulant. Thus, the flash problem in the prior art can be solved by means of the runners and grooves.

摘要翻译： 提出了一种引线框架半导体封装及其引线框架。 所述半导体封装包括：所述引线框架具有至少一个管芯焊盘和围绕所述管芯焊盘的多个引线，其中在所述管芯焊盘的表面上形成多个沟槽和流道，并且每个所述沟槽连接到 由至少一个跑步者的模具垫的边缘; 至少一个芯片安装在所述管芯焊盘的另一个表面上并电连接到所述多个引线; 以及用于封装芯片的密封剂，其中流道和凹槽从密封剂暴露出来。 因此，现有技术中的闪光灯问题可以通过滑道和槽来解决。

公开(公告)号：US06396129B1

公开(公告)日：2002-05-28

申请号：US09800361

申请日：2001-03-05

申请人： Chin-Yuan Hung ,  Chang-Fu Chen ,  Fu-Di Tang

发明人： Chin-Yuan Hung ,  Chang-Fu Chen ,  Fu-Di Tang

IPC分类号： H01L23495

CPC分类号： H01L24/32 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A leadframe with a dot array of silver-plated regions on die pad is proposed, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package. The proposed leadframe is characterized by that the front side of the die pad is partitioned into a centrally-located die-mounting area and a peripherally-located ground-wire bonding area; and wherein the die-mounting area is selectively silver-plated to form a dot array of silver-plated regions, while the peripheral area of the die pad is entirely silver-plated to form a silver-plated peripheral area. In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad. Owing to the provision of the dot array of silver-plated regions within the die-mounting area, it allows a better electrical coupling between the die pad and the inactive surface of the semiconductor chip than the conventional ring plating scheme so that the packaged semiconductor chip can have a better grounding effect, and also allows the silver-epoxy layer to be better adhered to the die pad than the conventional spotted plating scheme to prevent delamination.

摘要翻译： 提出了一种引线框架，其具有在芯片焊盘上的镀银区域的阵列阵列，其被专门设计用于暴露焊盘型半导体封装的构造。 所提出的引线框架的特征在于，芯片焊盘的前侧被分隔成中心定位的管芯安装区域和位于外围的接地引线接合区域; 并且其中，所述管芯安装区域被选择性地镀银以形成镀银区域的点阵列，同时所述管​​芯焊盘的周边区域被完全镀银以形成镀银周边区域。 此外，芯片焊盘的管芯安装区域可以进一步形成有多个凹坑，目的是增加管芯焊盘和待粘贴在管芯安装区域上的银环氧树脂层之间的接触面积 用于将半导体芯片粘附到管芯焊盘。 由于在芯片安装区域内设置镀银区域的点阵列，所以允许芯片焊盘和半导体芯片的非活性表面之间的电气耦合比传统的环形电镀方案更好地电连接，使得封装的半导体芯片 可以具有更好的接地效果，并且还允许银环氧树脂层比常规的点电镀方案更好地粘附到芯片焊盘，以防止分层。

公开(公告)号：US20110221059A1

公开(公告)日：2011-09-15

申请号：US12825513

申请日：2010-06-29

申请人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

发明人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC分类号： H01L23/49 ,  H01L21/60

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield.

摘要翻译： QFN封装包括芯片安装基座; 设置在芯片安装基座的周边周围的电连接焊盘，芯片安装基座的底面和电连接焊盘被铜层覆盖; 安装在芯片安装基座的顶表面上的芯片; 电连接到芯片和电连接焊盘的接合线; 在暴露铜层的同时封装芯片安装基座，电连接焊盘，芯片和接合线的密封剂; 以及形成在密封剂和铜层的底表面上并且具有暴露铜层的一部分的多个开口的电介质层。 铜层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片安装基座，电连接焊盘和电介质层之间的界面，从而避免焊料挤出并提高产品产量。

公开(公告)号：US20110221049A1

公开(公告)日：2011-09-15

申请号：US12843440

申请日：2010-07-26

申请人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

发明人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/552 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

摘要翻译： 四通道扁平无引线（QFN）半导体封装包括管芯焊盘; 设置在管芯焊盘周边的I / O连接; 安装在芯片焊盘上的芯片; 接合线; 用于封装芯片焊盘的密封剂，I / O连接，芯片和接合线，同时暴露管芯焊盘的底表面和I / O连接; 形成在管芯焊盘的底部表面上的表面层和I / O连接; 形成在密封剂和表面层的底表面上并具有用于暴露表面层的开口的电介质层。 表面层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片焊盘中并防止焊料挤出在I / O连接和电介质层的界面上，从而提高产品产量。

公开(公告)号：US07314820B2

公开(公告)日：2008-01-01

申请号：US11042939

申请日：2005-01-24

申请人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

发明人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/48 ,  H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/85001 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

摘要翻译： 提供了一种无载体半导体封装及其制造方法。 该制造方法包括以下步骤：提供其上形成有多个电触头的载体; 在载体上安装至少一个芯片; 通过多个接合线将芯片电连接到电触点; 在每个所述电触点上形成涂层，以将每个所述接合线的接合端封装在所述电触点上; 进行成型工艺以形成用于封装芯片，接合线和电触头的密封剂; 并移除载体，使得电触点的底表面从密封剂暴露出来。 这获得不具有载体的半导体封装，并且涂层可以增强电触点和密封剂之间的粘附。