公开(公告)号：US5434448A

公开(公告)日：1995-07-18

申请号：US307476

申请日：1994-09-16

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/82 ,  H01L23/525 ,  H01L29/41 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S257/915

摘要： A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

摘要翻译： 提供了可编程半导体接触结构和方法。 半导体衬底具有用于形成互连的第一图案化导电层。 第一绝缘层覆盖在第一图案化导电层上。 通过绝缘层形成开口到第一图案化导电层以形成接触通孔。 缓冲层覆盖第一绝缘层的部分并覆盖开口。 第二导电层覆盖缓冲层。 然后第三导电层覆盖集成电路。 缓冲层是诸如非晶硅的材料，其用作抗熔丝并且可以通过应用相对高的编程电压进行编程。

公开(公告)号：US5260229A

公开(公告)日：1993-11-09

申请号：US755508

申请日：1991-08-30

申请人： Robert L. Hodges ,  Frank R. Bryant ,  Fusen E. Chen ,  Che-Chia Wei

发明人： Robert L. Hodges ,  Frank R. Bryant ,  Fusen E. Chen ,  Che-Chia Wei

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76202 ,  H01L21/32

摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

公开(公告)号：US5166770A

公开(公告)日：1992-11-24

申请号：US38394

申请日：1987-04-15

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Cheng-Eng D. Chen

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Cheng-Eng D. Chen

IPC分类号： H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/285 ,  H01L23/53257 ,  H01L27/0928 ,  H01L2924/0002

摘要： Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.

摘要翻译： 优选实施例包括具有钛硅化物结（38,58）的硅互补MOSFET和铝金属化（61,62）与p结（58）的直接接触，避免了硅化物（60）对p硅（58）的高接触电阻 ）。 优选实施例还包括没有相应的硅化MOSFET结的硅化多晶硅线。

公开(公告)号：US5124280A

公开(公告)日：1992-06-23

申请号：US648554

申请日：1991-01-31

申请人： Che-Chia Wei ,  Fu-Tai Liou

发明人： Che-Chia Wei ,  Fu-Tai Liou

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53271 ,  H01L21/76889 ,  H01L21/76895 ,  H01L2924/0002

摘要： Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

公开(公告)号：US4690730A

公开(公告)日：1987-09-01

申请号：US876947

申请日：1986-06-20

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway ,  David A. Bell

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway ,  David A. Bell

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/76895 ,  H01L2924/0002

摘要： A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.

摘要翻译： 氧化物（或氧化物/氮化物）在反应步骤期间防止硅扩散，其形成直接反应的硅化钛。

公开(公告)号：US4676866A

公开(公告)日：1987-06-30

申请号：US837482

申请日：1986-03-07

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L27/11526 ,  H01L21/32053 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543

摘要： A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.

摘要翻译： 用于VLSI集成电路的局部互连系统。 在氮气气氛中暴露的山沟和栅极区域的自对准硅化过程中，整体形成导电氮化钛层。 然后将第二钛层整体沉积并再次反应，以增加氮化物层而不增加硅化物层的厚度。 对该导电层进行图案化和蚀刻，以提供局部互连，其平面电阻为10欧姆/平方，并且也蚀刻停止。 此外，这种局部互连级别允许接触与护城河边界不对准，因为氮化钛局部互连层可以从护壕向上叠加到场氧化物上，以提供用于接触孔的底部接触和扩散屏障 通过层间氧化物蚀刻。 这种局部互连功能可以满足埋入式接触能力的所有功能，并满足其他功能。

公开(公告)号：US5841195A

公开(公告)日：1998-11-24

申请号：US448703

申请日：1995-05-24

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

摘要翻译： 提供了一种用于在集成电路中形成接触通孔的方法。 首先，在集成电路中的绝缘层上形成第一缓冲层。 第一缓冲层具有与绝缘层不同的蚀刻速率。 然后在第一缓冲层上形成第二缓冲层，其中第二缓冲层具有比第一缓冲层快的蚀刻速率。 执行各向同性蚀刻以产生通过第二缓冲层和第一缓冲层的一部分的开口。 因为第二缓冲层比第一缓冲层蚀刻更快，所以可以控制开口的侧壁的倾斜。 然后进行各向异性蚀刻以完成接触通孔的形成。

公开(公告)号：US5610083A

公开(公告)日：1997-03-11

申请号：US650697

申请日：1996-05-20

申请人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

发明人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203

摘要： A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

摘要翻译： 已经开发了用于在SOI层中产生可以容易地并入MOSFET制造配方中的背栅极接触的工艺。 背栅极接触由蚀刻的沟槽组成，内衬绝缘体并填充有多晶硅。 多晶硅填充沟槽将半导体衬底电连接到覆盖的金属触点。

公开(公告)号：US5500557A

公开(公告)日：1996-03-19

申请号：US126673

申请日：1993-09-24

申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/53271 ,  H01L2924/0002

摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

摘要翻译： 用于制造集成电路的结构和方法，其提供残留导电材料的检测。 第一导电层沉积在集成电路上并被图案化以限定第一互连层。 然后在集成电路上形成绝缘层。 然后沉积和图案化第二导电层以限定第二互连层。 当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。 为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

公开(公告)号：US5313084A

公开(公告)日：1994-05-17

申请号：US891450

申请日：1992-05-29

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/540

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： A local interconnect structure for an integrated circuit is formed from a patterned refractory metal silicide. The local interconnect has an overlying oxide layer, which prevents part of the amorphous silicon used to form the interconnect from becoming silicided. This results in a local interconnect layer which has thinner silicide portions than silicide regions formed over adjacent source/drain regions and gate electrodes.

摘要翻译： 用于集成电路的局部互连结构由图案化的难熔金属硅化物形成。 局部互连具有覆盖的氧化物层，其防止用于形成互连的非晶硅的一部分变成硅化物。 这导致局部互连层，其具有比在相邻源极/漏极区域和栅电极上形成的硅化物区更薄的硅化物部分。