公开(公告)号：US20120244669A1

公开(公告)日：2012-09-27

申请号：US13053223

申请日：2011-03-22

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Abstract translation: 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽。 然后，在第一沟槽中形成第一金属层。 去除第二牺牲栅极以形成第二沟槽。 接下来，在第一沟槽和第二沟槽中形成第二金属层。 最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

公开(公告)号：USD661834S1

公开(公告)日：2012-06-12

申请号：US29396858

申请日：2011-07-07

Applicant: Chien-Ting Lin

Designer： Chien-Ting Lin

公开(公告)号：US08193050B2

公开(公告)日：2012-06-05

申请号：US12907016

申请日：2010-10-18

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/8238

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US08190303B2

公开(公告)日：2012-05-29

申请号：US12338006

申请日：2008-12-18

Applicant: Chung-Hsiung Lin ,  Chien-Ting Lin

Inventor： Chung-Hsiung Lin ,  Chien-Ting Lin

IPC: G06F19/00 ,  G05D23/00 ,  F28F27/00

CPC classification number: H05K7/207 ,  G05D23/1932 ,  G06F1/206 ,  G06F2200/201 ,  H01L23/34 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a system to dissipate heat in an information handling system includes a first heat-generating component adapted to process first data and a second heat-generating component adapted to process second data. The system also includes a cooling fluid guide including an electroactive material. The cooling fluid guide is adapted to change from a first shape to a second shape, in response to receiving a trigger voltage or in response to no longer receiving the trigger voltage. The system also includes a controller adapted to detect a data load processed at the second heat-generating component and, in response to detecting the data load, to cause the trigger voltage to be received at, or no longer received at, the cooling fluid guide. The cooling fluid guide is adapted to direct an increased portion of cooling fluid toward the first heat-generating component when the cooling fluid guide is in a form of the second shape, as compared to the first shape.

Abstract translation: 在特定实施例中，在信息处理系统中散热的系统包括适于处理第一数据的第一发热组件和适于处理第二数据的第二发热组件。 该系统还包括包括电活性材料的冷却流体引导件。 响应于接收到触发电压或响应于不再接收到触发电压，冷却流体引导件适于从第一形状变化到第二形状。 该系统还包括控制器，适于检测在第二发热部件处理的数据负载，并且响应于检测到数据负载，使得触发电压在冷却流体导向件处接收或不再接收 。 与第一形状相比，当冷却流体引导件处于第二形状的形式时，冷却流体引导件适于将增加的冷却流体部分引向第一发热部件。

公开(公告)号：US20110034019A1

公开(公告)日：2011-02-10

申请号：US12907016

申请日：2010-10-18

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/28

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US20110031558A1

公开(公告)日：2011-02-10

申请号：US12907036

申请日：2010-10-19

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L27/11

CPC classification number: H01L27/11

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract translation: 半导体器件的栅极结构包括第一低电阻导电层，第二低电阻导电层和设置在第一低电阻导电层和第二低电阻导电层的侧壁之间且直接接触的第一类型导电层。

公开(公告)号：US07838946B2

公开(公告)日：2010-11-23

申请号：US12058208

申请日：2008-03-28

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/76

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填满第一开口。

公开(公告)号：US20100207214A1

公开(公告)日：2010-08-19

申请号：US12372908

申请日：2009-02-18

Applicant: Chun-Fei Chuang ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Shao-Hua Hsu ,  Cheng-I Lin

Inventor： Chun-Fei Chuang ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Shao-Hua Hsu ,  Cheng-I Lin

IPC: H01L29/80 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device and a method of fabricating the same are described. A substrate having a PMOS area and an NMOS area is provided. A high-k layer is formed on the substrate. A first cap layer is formed on the high-k layer in the PMOS area, and a second cap layer is formed on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer. A metal layer and a polysilicon layer are sequentially formed on the first and second cap layers. The polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer are patterned to form first and second gate structures respectively in the PMOS and NMOS areas. First source/drain regions are formed in the substrate beside the first gate structure. Second source/drain regions are formed in the substrate beside the second gate structure.

Abstract translation: 对半导体器件及其制造方法进行说明。 提供具有PMOS区域和NMOS区域的衬底。 在基板上形成高k层。 在PMOS区域的高k层上形成第一覆盖层，在NMOS区域的高k层上形成第二覆盖层，其中第一覆盖层与第二覆盖层不同。 在第一和第二盖层上依次形成金属层和多晶硅层。 图案化多晶硅层，金属层，第一覆盖层，第二覆盖层和高k层，以在PMOS和NMOS区域中分别形成第一和第二栅极结构。 在第一栅极结构旁边的基板中形成第一源极/漏极区域。 第二源极/漏极区域形成在第二栅极结构旁边的衬底中。

公开(公告)号：US07608522B2

公开(公告)日：2009-10-27

申请号：US11684634

申请日：2007-03-11

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC: H01L21/30

CPC classification number: H01L21/02694 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02658 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

Abstract translation: 一种用于制造混合取向衬底的方法包括以下步骤：提供具有（100）结晶取向的第一衬底的直接硅键合（DSB）晶片和具有（110）结晶取向直接接合在第一衬底上的第二衬底，形成和图案化 在第二衬底上的第一阻挡层，以限定未被第一阻挡层覆盖的第一区域和由第一阻挡层覆盖的第二区域，执行非晶化过程以将第二衬底的第一区域变换为非晶化区域;以及 执行退火处理以使非晶化区域再结晶成第一衬底的取向并使第二区域受到第一阻挡层的应力。

公开(公告)号：US20090181504A1

公开(公告)日：2009-07-16

申请号：US12013485

申请日：2008-01-14

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Guang-Hwa Ma ,  Chin-Sheng Yang

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Guang-Hwa Ma ,  Chin-Sheng Yang

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7843

Abstract: A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.

Abstract translation: 一种用于制造CMOS器件的方法，包括：提供具有第一有源区和限定在其上的第二有源区的衬底，分别在第一和第二有源区中形成第一导电型晶体管和第二导电型晶体管，执行自对准硅化物工艺 ，形成ILD层，执行第一蚀刻工艺以去除第一导电型晶体管的第一栅极并形成开口，同时高K栅极电介质层暴露在开口的底部，并形成至少第一 金属层在开口。