公开(公告)号：US20060115774A1

公开(公告)日：2006-06-01

申请号：US10999625

申请日：2004-11-30

Applicant: Yu-Hsi Wang ,  Shi-Che Wang ,  Hua-Tal Lin ,  Shang Ho Lin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

Inventor： Yu-Hsi Wang ,  Shi-Che Wang ,  Hua-Tal Lin ,  Shang Ho Lin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/00

CPC classification number: G03F7/405 ,  H01L21/02057

Abstract: A novel method for eliminating or reducing the accumulation of electrostatic charges on semiconductor wafers during spin-rinse-drying of the wafers is disclosed. The method includes rinsing a wafer; applying an ionic solution to the wafer; and spin-drying the wafer. During the spin-drying step, the ionic solution neutralizes electrostatic charges on the wafer as the wafer is rotated. This reduces the formation of defects in devices fabricated on the wafer, as well as prevents or reduces electrostatic interference with processing equipment during photolithographic and other fabrication processes.

Abstract translation: 公开了一种用于在晶片的旋转冲洗干燥期间消除或减少半导体晶片上的静电电荷累积的新颖方法。 该方法包括冲洗晶片; 将离子溶液施加到晶片上; 并旋转晶片。 在旋转干燥步骤期间，当晶片旋转时，离子溶液中和晶片上的静电电荷。 这减少了在晶片上制造的器件中的缺陷的形成，以及在光刻和其它制造工艺期间防止或减少与处理设备的静电干扰。

公开(公告)号：US06998316B2

公开(公告)日：2006-02-14

申请号：US10708228

申请日：2004-02-18

Applicant: Tahorng Yang ,  Henry Chung ,  Cheng-Chen Calvin Hsueh ,  Ching-Yu Chang

Inventor： Tahorng Yang ,  Henry Chung ,  Cheng-Chen Calvin Hsueh ,  Ching-Yu Chang

IPC: H01L21/8236 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L27/1126 ,  H01L27/105 ,  H01L27/11293 ,  Y10S438/949

Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Abstract translation: 只读存储器的制造方法提供具有存储单元区域和外围电路区域的衬底。 存储单元区域具有存储单元阵列，并且外围电路区域具有晶体管。 在存储单元区域中形成具有多个第一开口的精确层。 第一开口在存储单元阵列中的每个存储单元的沟道区之上，并且第一开口的临界尺寸相同。 在基板上形成具有第二开口和第三开口的掩模层。 第二开口位于预编码存储单元区域上，并且第三开口位于晶体管栅极之上。 执行离子注入以对预编码存储单元区域中的存储单元进行编码，并使用精确层和掩模层作为掩模来调节晶体管的阈值电压。

公开(公告)号：US06960411B2

公开(公告)日：2005-11-01

申请号：US10314959

申请日：2002-12-10

Applicant: Yu-Lin Yen ,  Ching-Yu Chang ,  Shun-Li Lin

Inventor： Yu-Lin Yen ,  Ching-Yu Chang ,  Shun-Li Lin

IPC: G03F1/00 ,  G03F1/36 ,  H01L21/762 ,  G03F9/00

CPC classification number: G03F1/36 ,  H01L21/76224

Abstract: A mask with extended mask window for forming patterns on a semiconductor substrate. The mask includes a main chip array having four sides for forming patterns of a main chip in a semiconductor substrate and a plurality of extended mask windows arranged around the main chip array. A method of dummy exposure using the mask includes providing a semiconductor substrate comprising a nitride layer with a plurality of main chip areas therein, and a plurality of unpatterned areas therein, forming a resist layer on the semiconductor substrate, providing an exposure mask comprising a main chip array and a plurality of extended mask windows, patterning the main chip areas of the semiconductor substrate using the main chip array of the exposure mask, patterning the unpatterned areas of the semiconductor substrate using the windows of the exposure mask, and removing the unexposed portions of the resist layer.

Abstract translation: 具有用于在半导体衬底上形成图案的扩展掩模窗口的掩模。 掩模包括具有用于形成半导体衬底中的主芯片的图案的四个侧面的主芯片阵列和布置在主芯片阵列周围的多个扩展掩模窗口。 使用掩模的伪曝光方法包括提供包括其中具有多个主芯片区域的氮化物层和其中多个未图案化区域的半导体衬底，在半导体衬底上形成抗蚀剂层，提供包括主体的曝光掩模 芯片阵列和多个扩展掩模窗口，使用曝光掩模的主芯片阵列图案化半导体衬底的主芯片区域，使用曝光掩模的窗口对半导体衬底的未图案化区域进行图案化，以及去除未曝光部分 的抗蚀剂层。

公开(公告)号：US20050205108A1

公开(公告)日：2005-09-22

申请号：US10802087

申请日：2004-03-16

Applicant: Ching-Yu Chang ,  Chin-Hsiang Lin

Inventor： Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: A61N5/00 ,  B08B3/12 ,  B08B6/00 ,  B08B7/00 ,  B08B7/02 ,  G03B27/42 ,  G03F7/20 ,  G21G5/00

CPC classification number: G03F7/70341 ,  G03F7/70925

Abstract: A method and system for cleaning lens used in an immersion lithography system is disclosed. After positioning a wafer in the immersion lithography system, a light exposing operation is performed on the wafer using an objective lens immersed in a first fluid containing surfactant, wherein the surfactant reduces a likelihood for having floating defects adhere to the wafer and the objective lens.

Abstract translation: 公开了一种用于在浸没式光刻系统中使用的透镜的清洁方法和系统。 在将浸没光刻系统中的晶片定位之后，使用浸入第一流体表面活性剂中的物镜在晶片上进行曝光操作，其中表面活性剂减少浮动缺陷粘附到晶片和物镜的可能性。

公开(公告)号：US06887627B2

公开(公告)日：2005-05-03

申请号：US10132156

申请日：2002-04-26

Applicant: Henry Wei-Ming Chung ,  Chi-Yuan Hung ,  Ching-Yu Chang ,  I-Pien Wu

Inventor： Henry Wei-Ming Chung ,  Chi-Yuan Hung ,  Ching-Yu Chang ,  I-Pien Wu

IPC: G03F1/30 ,  G03F9/00

CPC classification number: G03F1/30

Abstract: A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.

Abstract translation: 描述了制造相移掩模（PSM）的方法。 在透明板上的不透明层上形成图案化的光致抗蚀剂层。 在图案化的光致抗蚀剂层的侧壁上形成薄的掩模层。 然后在使用图案化的光致抗蚀剂层和掩模层作为掩模的同时除去其下的暴露的不透明层和透明板。 在透明板中形成相移开口，由此在相移开口所在的位置形成相移层。 然后去除图案化的光致抗蚀剂层和其下的不透明层以暴露透明板。 掩模层下面的不透明层可以精确地自对准相移层，以防止由多个光刻工艺引起的对准偏差。 可以提高相移掩模的精度，并且可以降低掩模制造成本。

公开(公告)号：US06864185B2

公开(公告)日：2005-03-08

申请号：US10643000

申请日：2003-08-18

Applicant: Ta-Hung Yang ,  Chin-Cheng Yang ,  Ching-Yu Chang

Inventor： Ta-Hung Yang ,  Chin-Cheng Yang ,  Ching-Yu Chang

IPC: G03F7/20 ,  G03F7/26 ,  H01L21/302 ,  H01L21/461

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: A method of forming a feature pattern in a photosensitive layer includes forming the photosensitive layer on a substrate, providing a first mask having a first opaque area thereon, and performing a first exposure process with a first dose to form a first unexposed image in the photosensitive layer. The method further includes performing a second exposure process with a second dose to expose sidewalls of the first unexposed image so that the sidewalls of the first unexposed image receive at least a portion of the second dose thus forming a second unexposed image in the photosensitive layer, and developing the photosensitive layer with a developing process to form the feature pattern and to create features having smaller widths than those which would result in developing the photosensitive layer of the first unexposed image.

Abstract translation: 在感光层中形成特征图案的方法包括在基底上形成感光层，提供其上具有第一不透明区域的第一掩模，并且以第一剂量进行第一曝光处理以在感光层中形成第一未曝光图像 层。 该方法还包括用第二剂量进行第二曝光处理以暴露第一未曝光图像的侧壁，使得第一未曝光图像的侧壁接收第二剂量的至少一部分，从而在感光层中形成第二未曝光图像， 并用显影工艺显影感光层以形成特征图案，并产生具有比导致显影第一未曝光图像的感光层的那些宽度小的特征。

公开(公告)号：US06861176B2

公开(公告)日：2005-03-01

申请号：US10065003

申请日：2002-09-09

Applicant: Tsung-Hsien Wu ,  Ching-Yu Chang ,  Tahorng Yang

Inventor： Tsung-Hsien Wu ,  Ching-Yu Chang ,  Tahorng Yang

IPC: G03C5/00 ,  G03F1/00 ,  G03F1/36 ,  G03F9/00 ,  H01L21/027 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC classification number: G03F1/36 ,  H01L21/76802

Abstract: A method of forming holes in a layer through a cross-shape image exposure. The method includes removing a section from each corner of the rectangular patterns on a photomask to form cross-shape patterns so that circular or elliptical contact holes are formed on a photoresist layer after photo-exposure and development. Optical image contrast between contacts is increased by the cross-shape patterns on the photomask.

Abstract translation: 通过十字形图像曝光在层中形成孔的方法。 该方法包括从光掩模上的矩形图案的每个角落去除一部分以形成十字形图案，使得在曝光和显影之后在光致抗蚀剂层上形成圆形或椭圆形的接触孔。 通过光掩模上的交叉形状图案增加了触点之间的光学图像对比度。

公开(公告)号：US06802322B2

公开(公告)日：2004-10-12

申请号：US10063129

申请日：2002-03-25

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21302

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A stringer block is formed on the interface between a HDP silicon oxide layer and a silicon substrate. During an etching process for defining the profile of a floating gate, the stringer block functions to expose a bottom corner stringer. Following that, a polysilicon etching process effectively removes the bottom corner stringer. As a result, a stringerless flash memory cell is formed to prevent leakage currents, resulting from the bottom corner stringer, and improve both the reliability and data retention ability of the device.

Abstract translation: 在HDP氧化硅层和硅衬底之间的界面上形成纵梁块。 在用于限定浮动门的轮廓的蚀刻工艺期间，纵梁块用于暴露底部拐角桁条。 之后，多晶硅蚀刻工艺有效地去除了底角拐角。 结果，形成了一个无弯曲的快闪存储单元，以防止由底角拐角引起的漏电流，并提高设备的可靠性和数据保留能力。

公开(公告)号：US06689663B1

公开(公告)日：2004-02-10

申请号：US10218101

申请日：2002-08-12

Applicant: Ching-Yu Chang ,  Ta-Horng Yang

Inventor： Ching-Yu Chang ,  Ta-Horng Yang

IPC: H01L218246

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method of code programming a mask read only memory (ROM) is disclosed. According to the method, a first photoresist layer is formed over word lines and a gate oxide layer of a substrate already having implanted bit lines. The first photoresist layer is patterned to develop pre-code openings over all of the memory cells, which correspond to intersecting word and bit lines. The first photoresist layer is then hardened using either a treatment implant or a treatment plasma. Subsequently, a second photoresist layer is formed over the first photoresist layer and patterned to develop real-code openings over memory cells which are actually to be coded with a logic “0” value. Each memory cell to be coded is then implanted with implants passing through the pre-code openings and the real code openings and into the memory cell.

公开(公告)号：US06547647B2

公开(公告)日：2003-04-15

申请号：US09823994

申请日：2001-04-03

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: B24B100

CPC classification number: H01L21/02032 ,  B24B37/042

Abstract: A method of wafer reclaim, at least includes: provide a wafer; perform a first semiconductor process to let both film layer and numerous particles are formed on the wafer; perform chemical mechanical polishing process to let part of film layer is removed and scales of part of particles are decreased; perform wet etching process to let both residual film layer and residual particles are further removed; perform cleaning process to let surface of wafer is cleaned; and perform second semiconductor process to let a semiconductor structure is formed on wafer. Furthermore, concepts of the invention that both film layer and particles are thoroughly removed by both chemical mechanical polishing process and wet etching process can be applied as a method for cleaning wafer and a method for planarizing wafer.