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公开(公告)号：US20140084414A1
公开(公告)日：2014-03-27
申请号：US13629168
申请日：2012-09-27
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。
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22.发明申请公开(公告)号：US20100244252A1
公开(公告)日：2010-09-30
申请号：US12416131
申请日：2009-03-31
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76855 , H01L21/76867 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.
摘要翻译： 公开了在氟化低K电介质和Cu或Cu合金互连的界面处形成氟化物金属屏障的装置和方法。 氟化物金属屏障可以防止互连与氟化低K电介质反应。 该方法可以包括在氟化低K电介质上沉积金属或金属合金薄膜。 薄膜可以包括与来自氟化低K电介质的游离氟和/或氟化合物反应以形成氟化物金属屏障的金属或金属合金元素。
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公开(公告)号：US20100155887A1
公开(公告)日：2010-06-24
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译： 形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。 该过程包括将电容器单元边界的第一高度降低到第二高度。 普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。
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24.发明授权Shifter with automatic and manual shift modes and with shift position indicators 有权移位机具有自动和手动换档模式以及换档位置指示器公开(公告)号：US06568294B2
公开(公告)日：2003-05-27
申请号：US09788907
申请日：2001-02-20
IPC分类号： F16H5902
CPC分类号： G05G1/12 , F16H59/0204 , F16H63/42 , F16H2059/0239 , Y10T74/2003 , Y10T74/20043 , Y10T74/20067
摘要： A shifter includes a base and a shift lever pivoted to the base for movement along a single planar shift path. The single planar shift path includes a first portion having P, R, N, and D (i.e. an automatic-shift mode) and a second portion with 4, 3, 2, and 1 (i.e. a manual shift mode). A switch on the shift lever operates a solenoid for changing between an automatic shift mode where the first portion is operable, and a manual shift mode where the second portion is operable. A shift lever position indicator indicates a position of the shift lever in all its positions. The shift lever position indicator includes first and second polarized screens and a first and second polarized light sources arranged to selectively illuminate the first and second indicia when the shift lever is in the automatic or manual shift mode.
摘要翻译： 换档器包括基座和转动杆，该变速杆枢转到基座，以沿着单个平面移动路径移动。 单个平面移动路径包括具有P，R，N和D（即自动移位模式）的第一部分和具有3,4,3,2和1的第二部分（即手动移动模式）。 变速杆上的开关操作用于在第一部分可操作的自动变速模式和可操作第二部分的手动变速模式之间切换的螺线管。 变速杆位置指示器指示变速杆在其所有位置的位置。 换档杆位置指示器包括第一和第二偏振屏;以及第一和第二偏振光源，其布置成当换档杆处于自动或手动换档模式时选择性地照亮第一和第二标记。
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公开(公告)号：US09490313B2
公开(公告)日：2016-11-08
申请号：US14815149
申请日：2015-07-31
IPC分类号： H01L21/00 , H01L23/00 , H01L49/02 , H01L23/48 , H01L21/768 , H01L23/64 , H01L21/48 , H01L23/522
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
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公开(公告)号：US20150340424A1
公开(公告)日：2015-11-26
申请号：US14815149
申请日：2015-07-31
IPC分类号： H01L49/02 , H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。
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27.发明申请METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES 有权用于形成具有紧密间距互连结构的互连层的方法公开(公告)号：US20150214094A1
公开(公告)日：2015-07-30
申请号：US14163323
申请日：2014-01-24
申请人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
发明人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
IPC分类号： H01L21/768
CPC分类号： H01L21/7688 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76886 , H01L21/76897 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
摘要翻译： 用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。
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公开(公告)号：US20140312459A1
公开(公告)日：2014-10-23
申请号：US14319429
申请日：2014-06-30
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
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公开(公告)号：US08803283B2
公开(公告)日：2014-08-12
申请号：US13629168
申请日：2012-09-27
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。
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公开(公告)号：US20140210098A1
公开(公告)日：2014-07-31
申请号：US13753245
申请日：2013-01-29
申请人： Christopher J. Jezewski , Mauro J. Kobrinsky , Daniel Pantuso , Siddharth B. Bhingarde , Michael P. O'Day
发明人： Christopher J. Jezewski , Mauro J. Kobrinsky , Daniel Pantuso , Siddharth B. Bhingarde , Michael P. O'Day
IPC分类号： H01L23/00
CPC分类号： H01L23/562 , H01L23/293 , H01L23/481 , H01L23/522 , H01L23/5221 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/535 , H01L23/5381 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
摘要翻译： 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。
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