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    Memory cell having p-type pass device
    4.
    发明授权
    Memory cell having p-type pass device 有权
    具有p型通过装置的存储单元

    公开(公告)号：US07230842B2

    公开(公告)日：2007-06-12

    申请号：US11225912

    申请日：2005-09-13

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Nam Sung Kim ,  Yibin Ye ,  Vivek K. De ,  Kevin Zhang ,  Bo Zheng

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Nam Sung Kim ,  Yibin Ye ,  Vivek K. De ,  Kevin Zhang ,  Bo Zheng

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  Y10S257/903

    摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，一种装置包括耦合在单元电压节点和存储节点之间的第一p型装置，耦合在存储节点和参考电压节点之间的n型装置和耦合在第二p型装置之间 存储节点响应于选择线上的信号到位线。 衬底中的形成第一p型器件和第二p型器件的扩散区域的至少一侧基本对齐。 还公开了其他实施例。

    LTR/OBFF DESIGN SCHEME FOR ETHERNET ADAPTER APPLICATION
    8.
    发明申请
    LTR/OBFF DESIGN SCHEME FOR ETHERNET ADAPTER APPLICATION 审中-公开
    用于以太网适配器的LTR / OBFF设计方案

    公开(公告)号：US20160162421A1

    公开(公告)日：2016-06-09

    申请号：US14907649

    申请日：2013-08-07

    申请人： Xuhong XIONG ,  Kevin ZHANG ,  Xiaofeng YAN ,  Jack DU ,  QUALCOMM INCORPORATED

    发明人： Xuhong Xiong ,  Kevin Zhang ,  Xiaofeng Yan ,  Jack Du

    IPC分类号： G06F13/20 ,  G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/20 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/3808 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method of reducing power consumption in a computing platform is disclosed. An endpoint-device that is coupled to the computing platform includes a first data buffer and a second data buffer. The first data buffer buffers outgoing data to be transmitted to an external device via a first communications medium. The second data buffer buffers incoming data received from the external device via the first communications medium. At least one of the first or second data buffers may selectively communicate with the computing platform, via a second communications medium, during an active window of the other data buffer. The active window may be requested by the first and/or second data buffers based, at least in part, on a system idle signal. For some embodiments, the first communications medium is an Ethernet link. Further, for some embodiments, the second communications medium is a Peripheral Component Interconnect Express (PCIe) link.

    摘要翻译： 公开了一种降低计算平台功耗的方法。 耦合到计算平台的端点设备包括第一数据缓冲器和第二数据缓冲器。 第一数据缓冲器缓冲经由第一通信介质发送到外部设备的输出数据。 第二数据缓冲器缓冲经由第一通信介质从外部设备接收的输入数据。 第一或第二数据缓冲器中的至少一个可以在另一数据缓冲器的活动窗口期间经由第二通信介质选择性地与计算平台通信。 至少部分地基于系统空闲信号，可以由第一和/或第二数据缓冲器请求活动窗口。 对于一些实施例，第一通信介质是以太网链路。 此外，对于一些实施例，第二通信介质是外围组件互连Express（PCIe）链路。

    Bitline floating during non-access mode for memory arrays
    9.
    发明授权
    Bitline floating during non-access mode for memory arrays 有权
    位线在内存阵列的非访问模式下浮动

    公开(公告)号：US08982659B2

    公开(公告)日：2015-03-17

    申请号：US12645623

    申请日：2009-12-23

    申请人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    发明人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C11/413

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C11/413

    摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    摘要翻译： 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。