公开(公告)号：US07994010B2

公开(公告)日：2011-08-09

申请号：US11965415

申请日：2007-12-27

申请人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

发明人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66636

摘要： A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material.

摘要翻译： 用于制造诸如应变通道晶体管的半导体器件的工艺包括在靠近栅电极的衬底中形成外延区域，其中通过掩蔽邻近栅电极的侧壁间隔来限定外延区域的表面轮廓。 通过将外延材料沉积到选择性地蚀刻到栅电极的任一侧上的半导体衬底中的空腔中形成外延区域。 掩蔽侧壁间隔物限制了栅极附近的外延沉积材料的厚度，使得外延材料的上表面与半导体衬底的主表面基本上相同。 使用成角度的离子束在栅电极下方的沟道区域中形成掺杂区域，使得注入区域的掺杂分布基本上不受外延沉积材料中的表面不规则性的影响。

公开(公告)号：US20090184341A1

公开(公告)日：2009-07-23

申请号：US12009204

申请日：2008-01-17

申请人： Yung Fu Chong ,  Lee Wee Teo ,  Shyue Seng Tan ,  Chung Foong Tan

发明人： Yung Fu Chong ,  Lee Wee Teo ,  Shyue Seng Tan ,  Chung Foong Tan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is selectively formed over the STI and adjacent nFET regions to protect them during formation (e.g., reactive ion etching (RIE)) of the embedded source/drain (S/D) regions of the pFET. The mask also extends over the STI edge by a predetermined distance to cover a portion of the embedded S/D region disposed between the STI and gate structure. This helps protect or isolate the STI region during SiGe layer formation in the defined embedded S/D regions.

摘要翻译： 制造半导体器件的方法（和半导体器件）消除了嵌入式SiGe p型场效应晶体管（pFET）结构中的浅沟槽隔离（STI）凹槽。 这可以通过改善隔离度和降低由SiGe小面生长引起的漏电流和硅化物侵入STI来提高器件性能。 在STI和相邻的nFET区域上选择性地形成掩模以在pFET的嵌入式源极/漏极（S / D）区域的形成期间（例如，反应离子蚀刻（RIE））保护它们。 掩模也在STI边缘上延伸预定距离以覆盖设置在STI和栅极结构之间的嵌入式S / D区域的一部分。 这有助于在定义的嵌入式S / D区域中的SiGe层形成期间保护或隔离STI区域。

公开(公告)号：US08324031B2

公开(公告)日：2012-12-04

申请号：US12144652

申请日：2008-06-24

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Yung Fu Chong ,  Elgin Quek ,  Sanford Chu

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Yung Fu Chong ,  Elgin Quek ,  Sanford Chu

IPC分类号： H01L21/00

CPC分类号： H01L29/66537 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3223 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/532 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

摘要翻译： 提出了一种形成装置的方法。 该方法包括提供具有第一和第二区域的结构。 在第一和第二区域的至少一部分之间形成扩散阻挡层。 扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

公开(公告)号：US08119541B2

公开(公告)日：2012-02-21

申请号：US12510276

申请日：2009-07-28

申请人： Lee Wee Teo ,  Elgin Quek

发明人： Lee Wee Teo ,  Elgin Quek

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

公开(公告)号：US07888214B2

公开(公告)日：2011-02-15

申请号：US11302035

申请日：2005-12-13

申请人： Lee Wee Teo ,  Elgin Quek ,  Dong Kyun Sohn

发明人： Lee Wee Teo ,  Elgin Quek ,  Dong Kyun Sohn

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.

摘要翻译： 一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。 选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。 在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。 在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

公开(公告)号：US20090286365A1

公开(公告)日：2009-11-19

申请号：US12510276

申请日：2009-07-28

申请人： Lee Wee Teo ,  Elgin Quek

发明人： Lee Wee Teo ,  Elgin Quek

IPC分类号： H01L21/3205 ,  H01L21/268 ,  H01L21/322

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

公开(公告)号：US07592270B2

公开(公告)日：2009-09-22

申请号：US11940326

申请日：2007-11-15

申请人： Lee Wee Teo ,  Elgin Quek

发明人： Lee Wee Teo ,  Elgin Quek

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/469 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

公开(公告)号：US20080064191A1

公开(公告)日：2008-03-13

申请号：US11940326

申请日：2007-11-15

申请人： Lee Wee Teo ,  Elgin Quek

发明人： Lee Wee Teo ,  Elgin Quek

IPC分类号： H01L21/425

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

公开(公告)号：US20080166847A1

公开(公告)日：2008-07-10

申请号：US11763561

申请日：2007-06-15

申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。

公开(公告)号：US08647946B2

公开(公告)日：2014-02-11

申请号：US12621527

申请日：2009-11-19

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/42364 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/1045 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

摘要翻译： 公开了一种用于形成半导体器件的方法。 该方法包括提供用第二栅极结构制备的衬底。 在衬底上并在第二栅极上形成栅极间电介质。 还形成了第一道门。 第一栅极通过栅极间电介质相邻并与第二栅极分离。 图案化衬底以形成具有第一和第二相邻栅极的分离栅极结构。 分离栅极结构设置有与第一栅极相邻的电场均衡器。 电场均衡器在操作期间改善了第一栅极电场的均匀性。