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    Selective STI stress relaxation through ion implantation
    2.
    发明授权
    Selective STI stress relaxation through ion implantation 有权
    通过离子注入选择性STI应力松弛

    公开(公告)号：US08008744B2

    公开(公告)日：2011-08-30

    申请号：US12790975

    申请日：2010-05-31

    Applicant: Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    Inventor： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    IPC: H01L21/36

    CPC classification number: H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

    Abstract translation: 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。

    Modulation of stress in stress film through ion implantation and its application in stress memorization technique
    3.
    发明授权
    Modulation of stress in stress film through ion implantation and its application in stress memorization technique 有权
    通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用

    公开(公告)号：US08119541B2

    公开(公告)日：2012-02-21

    申请号：US12510276

    申请日：2009-07-28

    Applicant: Lee Wee Teo ,  Elgin Quek

    Inventor： Lee Wee Teo ,  Elgin Quek

    IPC: H01L21/469 ,  H01L21/31

    CPC classification number: H01L21/823807 ,  H01L21/823864

    Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

    Abstract translation: 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

    Strain-direct-on-insulator (SDOI) substrate and method of forming
    4.
    发明授权
    Strain-direct-on-insulator (SDOI) substrate and method of forming 有权
    绝缘体绝缘体（SDOI）基板及其成型方法

    公开(公告)号：US07998835B2

    公开(公告)日：2011-08-16

    申请号：US12008841

    申请日：2008-01-15

    Applicant: Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    Inventor： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    IPC: H01L21/30 ,  H01L21/46

    CPC classification number: H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

    Abstract: Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

    Abstract translation: 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

    Selective stress relaxation of contact etch stop layer through layout design
    5.
    发明授权
    Selective stress relaxation of contact etch stop layer through layout design 有权
    通过布局设计，接触蚀刻停止层的选择性应力松弛

    公开(公告)号：US07888214B2

    公开(公告)日：2011-02-15

    申请号：US11302035

    申请日：2005-12-13

    Applicant: Lee Wee Teo ,  Elgin Quek ,  Dong Kyun Sohn

    Inventor： Lee Wee Teo ,  Elgin Quek ,  Dong Kyun Sohn

    IPC: H01L21/336

    CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    Abstract: A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.

    Abstract translation: 一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。 选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。 在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。 在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

    Avoiding plasma charging in integrated circuits
    8.
    发明授权
    Avoiding plasma charging in integrated circuits 有权
    避免集成电路中的等离子体充电

    公开(公告)号：US07846800B2

    公开(公告)日：2010-12-07

    申请号：US12043148

    申请日：2008-03-06

    Applicant: Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

    Inventor： Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

    IPC: H01L21/336

    CPC classification number: H01L21/823857 ,  H01L27/0251 ,  H01L27/092

    Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.

    Abstract translation: 提供具有电路控制端子，初级电路和保护电路的电路。 初级电路包括厚度T1的初级控制端子和主栅极氧化物。 主控制端子耦合到电路控制端子。 具有保护控制端子的保护电路耦合到初级电路。 保护电路包括小于T1的第二厚度T2的保护栅极氧化物。 保护栅极氧化物减少了初级电路中的等离子体引起的损坏。

    Selective STI stress relaxation through ion implantation
    9.
    发明授权
    Selective STI stress relaxation through ion implantation 有权
    通过离子注入选择性STI应力松弛

    公开(公告)号：US07727856B2

    公开(公告)日：2010-06-01

    申请号：US11615980

    申请日：2006-12-24

    Applicant: Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    Inventor： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    IPC: H01L21/76

    CPC classification number: H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

    Abstract translation: 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。

    Modulation of Stress in Stress Film through Ion Implantation and Its Application in Stress Memorization Technique
    10.
    发明申请
    Modulation of Stress in Stress Film through Ion Implantation and Its Application in Stress Memorization Technique 有权
    通过离子注入调制应力薄膜的应力及其在应力记忆技术中的应用

    公开(公告)号：US20090286365A1

    公开(公告)日：2009-11-19

    申请号：US12510276

    申请日：2009-07-28

    Applicant: Lee Wee Teo ,  Elgin Quek

    Inventor： Lee Wee Teo ,  Elgin Quek

    IPC: H01L21/3205 ,  H01L21/268 ,  H01L21/322

    CPC classification number: H01L21/823807 ,  H01L21/823864

    Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

    Abstract translation: 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

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