公开(公告)号：US5650346A

公开(公告)日：1997-07-22

申请号：US557546

申请日：1995-11-14

Applicant: Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:forming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract translation: 一种MOSFET器件，其具有覆盖有介电材料的衬底，该器件包括电容耦合到多晶硅电极的多个掩埋导体，其通过以下方式制成：在包含MOSFET器件的区域之间形成通过离子注入穿过衬底中的多个位线的区域 栅极氧化物以预定图案进入衬底，并且在电介质材料上形成跨越位线的多晶硅电极。

公开(公告)号：US5554545A

公开(公告)日：1996-09-10

申请号：US299266

申请日：1994-09-01

Applicant: Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/822 ,  H01L27/115 ,  H01L21/265

CPC classification number: H01L27/115 ,  H01L21/8221 ,  H01L29/788 ,  Y10S148/116 ,  Y10S148/117 ,  Y10S148/163 ,  Y10S438/981

Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.

Abstract translation: 制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模 在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极 的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

公开(公告)号：US08357579B2

公开(公告)日：2013-01-22

申请号：US13042539

申请日：2011-03-08

Applicant: King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

Inventor： King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/76 ,  H01L21/02

CPC classification number: H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 去除基板的一部分以形成与栅极结构相邻的凹部。 在每个凹部的侧壁和底部形成有具有第一类型掺杂剂的富掺杂层。 在每个凹部中形成含硅材料结构。 含硅材料结构具有第二种掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20110248322A1

公开(公告)日：2011-10-13

申请号：US12758568

申请日：2010-04-12

Applicant: King-Yuen Wong ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

Inventor： King-Yuen Wong ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7843

Abstract: An embodiment is a semiconductor device. The semiconductor device comprises a substrate, an electrode over the substrate, and a piezoelectric layer disposed between the substrate and the electrode. The piezoelectric layer causes a strain in the substrate when an electric field is generated by the electrode.

Abstract translation: 一个实施例是半导体器件。 半导体器件包括衬底，衬底上的电极以及设置在衬底和电极之间的压电层。 当电极产生电场时，压电层在衬底中引起应变。

公开(公告)号：US20070224808A1

公开(公告)日：2007-09-27

申请号：US11387614

申请日：2006-03-23

Applicant: Tsung-Hsien Chang ,  Tung-Heng Hsieh ,  Chung-Cheng Wu ,  Shou Chang

Inventor： Tsung-Hsien Chang ,  Tung-Heng Hsieh ,  Chung-Cheng Wu ,  Shou Chang

IPC: H01L21/4763

CPC classification number: H01L29/665 ,  H01L21/31111 ,  H01L29/6653

Abstract: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer is etched to form spacers adjacent the gate electrode. A treatment is performed on the first dielectric layer over the gate electrode, wherein the treatment increases the effective etch rate of the first dielectric layer as compared to untreated portions of the first dielectric layer. An etching procedure is then performed to expose the surface of the gate electrode, the etching procedure recessing the liner along sidewalls of the gate electrode. Thereafter, a silicide procedure is performed to silicide at least a portion of the gate electrode.

Abstract translation: 提供了用于CMOS晶体管的硅化物栅极和制造方法。 在基板上形成栅电极。 在栅电极和衬底之上形成第一电介质层，并且在第一介电层上形成第二电介质层。 蚀刻第二电介质层以形成邻近栅极的间隔物。 在栅电极上的第一电介质层上进行处理，其中与第一介电层的未处理部分相比，处理增加了第一介电层的有效蚀刻速率。 然后执行蚀刻过程以暴露栅电极的表面，蚀刻过程使衬垫沿着栅电极的侧壁凹陷。 此后，执行硅化物步骤以对栅电极的至少一部分进行硅化。

公开(公告)号：US20060055289A1

公开(公告)日：2006-03-16

申请号：US10937326

申请日：2004-09-10

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: A47G29/00

CPC classification number: F16B12/32 ,  A47B47/0016 ,  A47F7/0078 ,  A47G7/041

Abstract: A combinational gardening rack comprising several frames, several combining connectors and a hood; the major feature of the present invention is that the combining connectors have vertical and horizontal connecting holes with same diameter, the vertical connecting hole is hollow in center, a wedge stretches out from the bottom of the vertical connecting hole, a locking mechanism is on the wedge. While assembly based on the structure described above, users can apply the wedges and locking mechanisms to assemble the frames and the combining connectors together at any height on the vertical frames, such scheme can adjust the height between layers of the rack.

Abstract translation: 组合式园艺架，包括几个框架，多个组合连接器和罩; 本发明的主要特征在于，组合连接器具有直径相同的垂直和水平连接孔，垂直连接孔在中心是中空的，楔形件从垂直连接孔的底部伸出，锁定机构位于 楔。 在基于上述结构的组装时，用户可以应用楔形和锁定机构将框架和组合连接器组装在垂直框架上的任何高度处，这种方案可以调节机架的层之间的高度。

公开(公告)号：US20050012087A1

公开(公告)日：2005-01-20

申请号：US10619828

申请日：2003-07-15

Applicant: Yi-Ming Sheu ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Chung-Cheng Wu

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/26533 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A transistor device having a strained channel and a method for forming the transistor device are disclosed. The transistor device includes a semiconductor region having a top surface. The transistor device includes a source region, a drain region, and a channel region in the semiconductor region. The channel region is between the source region and the drain region. The transistor device includes an oxide region within the channel region and a gate overlying the channel region. The oxide region is laterally spaced from the source and drain regions. The transistor device includes a gate dielectric between the gate and the channel region.

Abstract translation: 公开了具有应变通道的晶体管器件和用于形成晶体管器件的方法。 晶体管器件包括具有顶表面的半导体区域。 晶体管器件包括半导体区域中的源极区域，漏极区域和沟道区域。 沟道区域在源极区域和漏极区域之间。 晶体管器件包括沟道区域内的氧化物区域和覆盖沟道区域的栅极。 氧化物区域与源极区域和漏极区域横向间隔开。 晶体管器件包括在栅极和沟道区域之间的栅极电介质。

公开(公告)号：US06583014B1

公开(公告)日：2003-06-24

申请号：US10246251

申请日：2002-09-18

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01K21336

CPC classification number: H01L29/42392 ,  H01L29/0657 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract translation: 水平周围栅极MOSFET包括形成在半导体衬底的上硅层中的整体结构，其基本上是绝缘体上硅（SOI）晶片，所述整体结构包括相对地设置在圆柱形 通道区域纵向设置在源极和漏极之间。 通道被栅极电介质覆盖，并且环形栅电极沿周向覆盖通道。

公开(公告)号：US06175394B1

公开(公告)日：2001-01-16

申请号：US08760101

申请日：1996-12-03

Applicant: Chung-Cheng Wu ,  Wen-Jyh Sah

Inventor： Chung-Cheng Wu ,  Wen-Jyh Sah

IPC: G02F1136

CPC classification number: H01L29/78696 ,  G02F1/136204 ,  H01L27/12

Abstract: A flat panel display includes a plurality of parallel row select lines and a plurality of column drive lines, with the row select lines and the column drive lines intersecting to define a matrix of pixel locations. Signals are provided to contact pads located on the periphery of the display and the signals flow over the row select lines and the column drive lines to thin film transistors located adjacent a pixel electrode at each of the pixel locations. The signals provided to each thin film transistor cause the transistor to charge a corresponding pixel electrode to control a pixel of the display. ESD protection for the display comprises a guard ring adjacent the contact pads. Capacitively coupled field effect transistors (CCFETs) connect the row select lines to the guard ring and connect the column drive lines to the guard ring. A CCFET is formed as a thin film transistor and typically has a floating gate capacitively coupled to the drain and source of the thin film transistor.

Abstract translation: 平板显示器包括多个平行的行选择线和多个列驱动线，其中行选择线和列驱动线相交以限定像素位置的矩阵。 信号被提供给位于显示器周边的接触焊盘，并且信号流过行选择线和列驱动线到位于每个像素位置处的像素电极附近的薄膜晶体管。 提供给每个薄膜晶体管的信号导致晶体管对相应的像素电极充电以控制显示器的像素。 用于显示器的ESD保护包括与接触垫相邻的保护环。 电容耦合场效应晶体管（CCFET）将行选择线连接到保护环，并将列驱动线连接到保护环。 CCFET形成为薄膜晶体管，并且通常具有电容耦合到薄膜晶体管的漏极和源极的浮动栅极。

公开(公告)号：US6164562A

公开(公告)日：2000-12-26

申请号：US449909

申请日：1999-12-02

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: B05B3/04

CPC classification number: B05B3/0436 ,  Y10T137/86847

Abstract: A rotary type swingable sprayer comprising a fixing tube head, a rotatable tube head, and a nozzle tube. The rotatable tube head is installed atop the fixing tube head, and the nozzle tube is installed atop the rotatable tube head. The lower end of the fixing tube head is connected with a water tube for guiding water. When water flows through the rotatable tube head, the rotatable tube head will swing nearly a full cycle repeatedly so as to drive the nozzle tube above to swing repeatedly. Thus, water is jetted out from the distal end of the nozzle tube. Therefore, water is sprayed out nearly through a full cycle in the whole area.

Abstract translation: 一种旋转式可摆动喷雾器，包括固定管头，可旋转管头和喷嘴管。 可旋转管头安装在固定管头的顶部，喷嘴管安装在可旋转管头的顶部。 固定管头的下端与用于引导水的水管连接。 当水流过可旋转的管头时，可旋转的管头将重复地摆动几乎整个周期，以便将喷嘴管驱动到上方以重复摆动。 因此，从喷嘴管的远端喷出水。 因此，在整个地区几乎完全喷洒水。