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    Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method
    21.
    发明申请
    Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method 有权
    用于切换高于设备制造技术的标称电位的高电位的递归设备及相关系统和方法

    公开(公告)号：US20070171696A1

    公开(公告)日：2007-07-26

    申请号：US11643009

    申请日：2006-12-19

    Applicant: Cyrille Dray ,  Stephane Gamet

    Inventor： Cyrille Dray ,  Stephane Gamet

    IPC: G11C11/22

    CPC classification number: H03K17/102 ,  H03K17/693

    Abstract: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n−1 potentials ranked 1 to n−1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.

    Abstract translation: 本发明的一个实施例涉及第n个订单选择器开关装置，包括：第一臂，包括串联连接在施加0级电位的第一输入和输出之间的n个晶体管; 以及第二臂，包括串联连接在施加0级电位的第二输入和输出之间的n个晶体管。 根据本发明的装置还包括：产生潜在排名0和潜在等级为n之间的包括1至n-1的n-1个电位的装置; 以及用于从适于驱动第一臂的晶体管的栅极和第二臂的晶体管的栅极的控制信号产生从0到n的n + 1个电位的驱动装置，使得一个晶体管 根据相对于0级电位值的n级势的值，另一臂的晶体管截止。

    LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY
    24.
    发明申请
    LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY 有权
    用于改善非易失性存储器的读取和写入操作的低电阻位线和电源设备

    公开(公告)号：US20150117095A1

    公开(公告)日：2015-04-30

    申请号：US14129506

    申请日：2013-10-31

    Applicant: Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

    Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

    Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

    Memory with intervening transistor
    26.
    发明授权
    Memory with intervening transistor 有权
    具有中间晶体管的存储器

    公开(公告)号：US08243490B2

    公开(公告)日：2012-08-14

    申请号：US12627751

    申请日：2009-11-30

    Applicant: Cyrille Dray

    Inventor： Cyrille Dray

    IPC: G11C5/06

    CPC classification number: G11C16/02 ,  G11C8/14

    Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

    Abstract translation: 这里公开的是存储器件和相关的方法和技术。 存储器件中的单元可以与中间晶体管相关联，所述中间晶体管被配置为在第一操作条件下隔离所述单元与相邻单元，并且在第二操作条件下向与所述单元相关联的位线提供电流。

    Memory With Intervening Transistor
    27.
    发明申请
    Memory With Intervening Transistor 有权
    存储器与中间晶体管

    公开(公告)号：US20110128767A1

    公开(公告)日：2011-06-02

    申请号：US12627751

    申请日：2009-11-30

    Applicant: Cyrille Dray

    Inventor： Cyrille Dray

    IPC: G11C5/06 ,  H01L27/105

    CPC classification number: G11C16/02 ,  G11C8/14

    Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

    Abstract translation: 这里公开的是存储器件和相关的方法和技术。 存储器件中的单元可以与中间晶体管相关联，所述中间晶体管被配置为在第一操作条件下隔离所述单元与相邻单元，并且在第二操作条件下向与所述单元相关联的位线提供电流。

    Column redundancy system for an integrated circuit memory
    28.
    发明授权
    Column redundancy system for an integrated circuit memory 有权
    集成电路存储器的列冗余系统

    公开(公告)号：US07391661B2

    公开(公告)日：2008-06-24

    申请号：US11484343

    申请日：2006-07-11

    Applicant: Cyrille Dray

    Inventor： Cyrille Dray

    IPC: G11C7/02

    CPC classification number: G11C29/848

    Abstract: A memory is organized with many memory subspaces (db ) each including their own read-out circuit (SA ). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD ) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.

    Abstract translation: 存储器被组织有许多存储器子空间（db ），每个存储器子空间包括它们自己的读出电路（SA i）。 在每个子空间内提供至少一个冗余列（Blred），以补偿所述子空间的至少一个缺陷列。 提供存储器控制器用于经由写总线（TD）和读总线（Q）与存储器进行交互。 存储器控制器产生用于启用冗余列的信号（TD i）。 该信号被提供以便被传送到写总线（TD）连接到的存储器的读出电路。 因此，经由读出电路使得能够与缺陷列地址相关联的存储器子空间的冗余列。

    Magnetic random access memory array having bit/word lines for shared write select and read operations
    29.
    发明授权
    Magnetic random access memory array having bit/word lines for shared write select and read operations 有权
    具有用于共享写入选择和读取操作的位/字线的磁性随机存取存储器阵列

    公开(公告)号：US07209383B2

    公开(公告)日：2007-04-24

    申请号：US11159858

    申请日：2005-06-23

    Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

    Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

    IPC: G11C11/14

    CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

    Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

    Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

    Column redundancy system for an integrated circuit memory
    30.
    发明申请
    Column redundancy system for an integrated circuit memory 有权
    集成电路存储器的列冗余系统

    公开(公告)号：US20070033450A1

    公开(公告)日：2007-02-08

    申请号：US11484343

    申请日：2006-07-11

    Applicant: Cyrille Dray

    Inventor： Cyrille Dray

    IPC: G11C29/00

    CPC classification number: G11C29/848

    Abstract: A memory is organized with many memory subspaces (db ) each including their own read-out circuit (SA ). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD ) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.

    Abstract translation: 存储器被组织有许多存储器子空间（db ），每个存储器子空间包括它们自己的读出电路（SA i）。 在每个子空间内提供至少一个冗余列（Blred），以补偿所述子空间的至少一个缺陷列。 提供存储器控制器用于经由写总线（TD）和读总线（Q）与存储器进行交互。 存储器控制器产生用于启用冗余列的信号（TD i）。 该信号被提供以便被传送到写总线（TD）连接到的存储器的读出电路。 因此，经由读出电路使得能够与缺陷列地址相关联的存储器子空间的冗余列。

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