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21.发明申请公开(公告)号：US20190266508A1
公开(公告)日：2019-08-29
申请号：US16275816
申请日：2019-02-14
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Yu Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US10268622B2
公开(公告)日：2019-04-23
申请号：US15418497
申请日：2017-01-27
Applicant: D-Wave Systems Inc.
Inventor： Jeremy P. Hilton , Aidan Patrick Roy , Paul I. Bunyk , Andrew Douglas King , Kelly T. R. Boothby , Richard G. Harris , Chunqing Deng
Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
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23.发明申请公开(公告)号：US20180101786A1
公开(公告)日：2018-04-12
申请号：US15726239
申请日：2017-10-05
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
CPC classification number: G06N10/00 , H01L39/02 , H01L39/22 , H01L39/223 , H03M1/1009 , H03M1/66
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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24.发明授权公开(公告)号：US12039407B2
公开(公告)日：2024-07-16
申请号：US18203880
申请日：2023-05-31
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Kelly T. R. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
CPC classification number: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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公开(公告)号：US11861455B2
公开(公告)日：2024-01-02
申请号：US16858108
申请日：2020-04-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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Patent Agency Ranking
公开(公告)号：US11507871B2
公开(公告)日：2022-11-22
申请号：US16307382
申请日：2017-06-07
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby , Paul I. Bunyk
Abstract: Topologies for analog computing systems may include cells of qubits which may implement a tripartite graph and cross substantially orthogonally. Qubits may have an H-shape or an l-shape, qubits may change direction within a cell. Topologies may be comprised of two or more different sub-topologies. Qubits may be communicatively coupled to non-adjacent cells by long-range couplers. Long-range couplers may change direction within a cell. A cell may have two or more different type of long-range couplers. A cell may have shifted qubits, more than one type of inter-cell couplers, more than one type of intra-cell couplers and long-range couplers.
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27.发明申请公开(公告)号：US20220335320A1
公开(公告)日：2022-10-20
申请号：US17739411
申请日：2022-05-09
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Kelly T. R. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
IPC: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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28.发明申请公开(公告)号：US20220019929A1
公开(公告)日：2022-01-20
申请号：US17387654
申请日：2021-07-28
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US11138511B2
公开(公告)日：2021-10-05
申请号：US15846538
申请日：2017-12-19
Applicant: D-Wave Systems Inc.
Inventor： Sheir Yarkoni , Kelly T. R. Boothby , Adam Douglass
Abstract: Quantum annealers as analog or quantum processors can find paths in problem graphs embedded in a hardware graph of the processor, for example finding valid paths, shortest paths or longest paths. A set of input, for example nucleic acid reads, can be used to set up a graph with edges between nodes denoting overlap (i.e., common base pairs) between the reads with constraints applied to perform sequence alignment or sequencing of a nucleic acid (e.g., DNA) strand or sequence, finding a solution that has a ground state energy. At least a portion of the described approaches can be applied to other problems, for instance resource allocations problems, e.g., job scheduling problems, traveling salesperson problems, and other NP-complete problems.
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30.发明申请公开(公告)号：US20210013391A1
公开(公告)日：2021-01-14
申请号：US16098801
申请日：2017-05-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E.S. Johansson
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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