公开(公告)号：US07968870B2

公开(公告)日：2011-06-28

申请号：US12076048

申请日：2008-03-13

申请人： Chul-Kyu Kang ,  Jong-Hyun Choi ,  Woo-Sik Jun ,  Hee-Chul Jeon

发明人： Chul-Kyu Kang ,  Jong-Hyun Choi ,  Woo-Sik Jun ,  Hee-Chul Jeon

IPC分类号： H01L51/52

CPC分类号： H01L29/41733 ,  H01L27/12 ,  H01L27/124 ,  H01L27/3244

摘要： A thin film transistor, e.g., for use in an organic light emitting display, may include: a gate insulating layer disposed on a gate electrode located on a substrate; a semiconductor layer, disposed on the gate insulating layer; and a planarization layer disposed on the gate insulating layer, the source and drain electrodes, and the channel area, and having openings exposing parts of the first source and drain areas and the source and drain electrodes, respectively. The semiconductor layer may include: a channel area corresponding to the gate electrode; first source and drain areas doped with an impurity outside the channel area; second source and drain areas, including a metal, outside the first source and drain areas; and source and drain electrodes disposed on the second source and drain areas and exposing the first source and drain areas. A pixel electrode may be disposed in one of the openings.

摘要翻译： 例如，用于有机发光显示器的薄膜晶体管可以包括：栅极绝缘层，设置在位于衬底上的栅电极上; 半导体层，设置在所述栅极绝缘层上; 以及设置在所述栅极绝缘层，所述源极和漏极以及所述沟道区上的平坦化层，并且具有分别暴露所述第一源极和漏极区域以及所述源极和漏极的部分的开口。 半导体层可以包括：对应于栅电极的沟道区; 在沟道区域外掺杂杂质的第一源区和漏区; 第二源和漏区，包括金属，在第一源和漏区外; 以及设置在第二源极和漏极区域上并且暴露第一源极和漏极区域的源极和漏极电极。 像素电极可以设置在其中一个开口中。

公开(公告)号：US20110103166A1

公开(公告)日：2011-05-05

申请号：US12987539

申请日：2011-01-10

申请人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C7/06 ,  H03F3/68 ,  H03F3/16 ,  G06F17/50

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

公开(公告)号：US07928439B2

公开(公告)日：2011-04-19

申请号：US12149580

申请日：2008-05-05

申请人： Hee-Chul Jeon ,  Chul-Kyu Kang ,  Woo-Sik Jun ,  Jong-Hyun Choi

发明人： Hee-Chul Jeon ,  Chul-Kyu Kang ,  Woo-Sik Jun ,  Jong-Hyun Choi

IPC分类号： H01L29/04

CPC分类号： H01L27/3244 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733

摘要： A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the gate electrode, a plurality of doped areas proximate to the channel area, and a plurality of non-doped areas. Source and drain electrodes may be on the top surface of the semiconductor layer aligned above respective ones of the plurality of non-doped areas of the semiconductor layer. A planarization layer may be on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, and may include a plurality of openings respectively exposing the plurality of doped areas of the semiconductor layer and a portion of the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管（TFT）可以包括衬底，衬底上的栅极电极，栅电极上的栅极绝缘层和栅极绝缘层上的半导体层。 半导体层可以包括顶表面，在垂直方向上与栅极电极对准的沟道区域，靠近沟道区域的多个掺杂区域以及多个非掺杂区域。 源电极和漏电极可以在半导体层的顶表面上对准半导体层的多个非掺杂区域中的相应一个上方。 平坦化层可以在栅极绝缘层，源极和漏极以及半导体层沟道区上，并且可以包括分别暴露半导体层的多个掺杂区域和源电极的一部分的多个开口 漏电极。

公开(公告)号：US20110049507A1

公开(公告)日：2011-03-03

申请号：US12805701

申请日：2010-08-16

申请人： Jong-Hyun Choi

发明人： Jong-Hyun Choi

IPC分类号： H01L33/00 ,  H01L21/02 ,  H01L51/50

CPC分类号： H01L27/1251 ,  H01L27/1225

摘要： A display and a method of manufacturing the same, the display including a substrate main body, a first thin film transistor on the substrate main body, the first thin film transistor including a first gate electrode, the first gate electrode including polycrystalline silicon, a first semiconductor layer on the first gate electrode, first source electrode, and a first drain electrode, and a second thin film transistor on the substrate main body, the second thin film transistor including a second semiconductor layer, the second semiconductor layer including polycrystalline silicon and being on a same plane as the first gate electrode, a second gate electrode on the second semiconductor layer, a second source electrode, and a second drain electrode.

摘要翻译： 一种显示器及其制造方法，所述显示器包括基板主体，在所述基板主体上的第一薄膜晶体管，所述第一薄膜晶体管包括第一栅电极，所述第一栅电极包括多晶硅，第一 半导体层，第一栅电极，第一源极和第一漏电极以及基板主体上的第二薄膜晶体管，第二薄膜晶体管包括第二半导体层，第二半导体层包括多晶硅， 在与第一栅电极相同的平面上，在第二半导体层上的第二栅电极，第二源电极和第二漏电极。

公开(公告)号：US07869239B2

公开(公告)日：2011-01-11

申请号：US12078724

申请日：2008-04-03

申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C5/02

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

公开(公告)号：US07843752B2

公开(公告)日：2010-11-30

申请号：US12111468

申请日：2008-04-29

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/04

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07821007B2

公开(公告)日：2010-10-26

申请号：US11971191

申请日：2008-01-08

申请人： Jong-Hyun Choi

发明人： Jong-Hyun Choi

IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/78675 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

摘要： A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.

摘要翻译： 提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示装置。 根据该方法，可以通过一个掺杂工艺制造低电阻区域和高电阻区域。 薄膜晶体管包括：基板; 设置在所述基板上并且包括源极和漏极区域的半导体层，小于所述源极和漏极区域的高电阻区域，沟道区域和设置在所述高电阻区域和所述沟道区域之间的连接区域; 设置在所述半导体层上的栅极绝缘层; 设置在所述沟道区域上方的所述栅极绝缘层上的栅电极; 设置在所述栅电极上的层间绝缘层; 以及设置在层间绝缘层上并分别与源极和漏极区电连接的源极和漏极。

公开(公告)号：US20100246300A1

公开(公告)日：2010-09-30

申请号：US12731749

申请日：2010-03-25

申请人： Jong-Hyun Choi ,  Sang-Seok Kang

发明人： Jong-Hyun Choi ,  Sang-Seok Kang

IPC分类号： G11C29/00 ,  G11C7/12

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。

公开(公告)号：US20090302332A1

公开(公告)日：2009-12-10

申请号：US12475136

申请日：2009-05-29

申请人： Chul-Kyu Kang ,  Do-Hyun Kwon ,  Ju-Won Yoon ,  Jong-Hyun Choi ,  Jun-woo Lee

发明人： Chul-Kyu Kang ,  Do-Hyun Kwon ,  Ju-Won Yoon ,  Jong-Hyun Choi ,  Jun-woo Lee

IPC分类号： H01L33/00 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1255 ,  H01L29/4908

摘要： A flat panel display including a semiconductor circuit, and a method of manufacturing the semiconductor circuit are disclosed. In one embodiment, the semiconductor circuit includes i) a substrate, ii) a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive, iii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iv) a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer, and v) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode.

摘要翻译： 公开了一种包括半导体电路的平板显示器和制造该半导体电路的方法。 在一个实施例中，半导体电路包括i）衬底，ii）形成在衬底上的半导体层和第一电容器电极，第一电容器电极被掺杂为导电，iii）覆盖半导体层和第一 电容器电极，iv）设置在所述绝缘层上并对应于所述半导体层的一部分的栅电极，以及v）设置在所述绝缘层上并对应于所述第一电容器电极的第二电容器电极，其中所述栅电极比 第二电容器电极。

公开(公告)号：US07558128B2

公开(公告)日：2009-07-07

申请号：US11473402

申请日：2006-06-24

申请人： Chang-Ho Shin ,  Jong-Hyun Choi

发明人： Chang-Ho Shin ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array internal voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit internal voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

摘要翻译： 一种半导体存储器件，包括用于产生单元阵列参考电压的单元阵列内部电压产生电路和来自第一外部电源电压的单元阵列内部电压，用于产生外围电路参考电压的外围电路内部电压产生电路和外部电路内部电路的外围电路 来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。