公开(公告)号：US07676650B2

公开(公告)日：2010-03-09

申请号：US10347193

申请日：2003-01-21

申请人： Masaki Ukai

发明人： Masaki Ukai

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3814

摘要： When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer storing a logically and immediately preceding instruction, not the instruction in the other instruction buffer, to the specific instruction buffer without the instruction in the other instruction buffer, and a loop is generated by instruction buffers, thereby performing a short loop in an instruction buffer system capable of arbitrarily connecting a plurality of instruction buffers.

摘要翻译： 当存储在特定指令缓冲器中的指令与存储在另一指令缓冲器中的逻辑相同并且在逻辑上在特定指令缓冲器中的指令之后，从存储逻辑和紧接在前指令的指令缓冲器进行连接，而不是 在另一个指令缓冲器中的指令，而没有指令在另一个指令缓冲器中的特定指令缓冲器，并且循环由指令缓冲器产生，从而在能够任意连接多个指令缓冲器的指令缓冲器系统中执行短循环。

公开(公告)号：US07622525B2

公开(公告)日：2009-11-24

申请号：US10568072

申请日：2004-08-12

申请人： Masaki Ukai ,  Hitoshi Ohno ,  Koichiro Masunaga ,  Mutsuhisa Miyamoto ,  Kazunobu Takami

发明人： Masaki Ukai ,  Hitoshi Ohno ,  Koichiro Masunaga ,  Mutsuhisa Miyamoto ,  Kazunobu Takami

IPC分类号： C08L31/00 ,  C08L33/06 ,  C08L27/06 ,  C08K5/101

CPC分类号： C09K3/10 ,  C08K5/10

摘要： A two-pack curable composition of the present invention comprises plastisol liquid A which comppounds a thermoplastic resin and a plasticizer, and liquid B which compounds a gelling agent and is characterized in that it has a sprayable viscosity when liquids A and B are mixed and gels within 30 seconds to 60 minutes after application. This two-pack curable composition can be applied in a body-welding step of an automobile manufacturing line as a body or seam sealer (for water-proofing, air-tightness, dust-proofing or rust-prevention of welded areas), an underbody coating (for anti-chipping), or an adhesive.

摘要翻译： 本发明的双组分可固化组合物包含组合热塑性树脂的增塑溶胶液A和增塑剂，以及混合胶凝剂的液体B，其特征在于当液体A和B混合时具有可喷雾粘度，并且凝胶 应用后30秒至60分钟。 这种双组分固化性组合物可以应用于汽车生产线的车身焊接步骤中作为主体或接缝密封剂（用于防水，气密性，防尘或防止焊接区域），底部 涂层（用于防止切屑）或粘合剂。

公开(公告)号：US07246204B2

公开(公告)日：2007-07-17

申请号：US10368751

申请日：2003-02-20

申请人： Yuji Shirahige ,  Tsuyoshi Motokurumada ,  Masaki Ukai ,  Aiichiro Inoue

发明人： Yuji Shirahige ,  Tsuyoshi Motokurumada ,  Masaki Ukai ,  Aiichiro Inoue

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6024 ,  G06F2212/6026

摘要： The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

摘要翻译： 本发明基于高精度预测实现预取。 基于先前的存储器访问，预先在预取地址队列中预先登记多个地址值。 如果来自请求地址寄存器的处理器单元的请求地址与该地址值匹配，则通过将块大小加到请求地址而获得的预取地址作为预取请求被输出到二级高速缓存。 该预取地址将被写回预取地址队列。

公开(公告)号：US07007136B2

公开(公告)日：2006-02-28

申请号：US10341456

申请日：2003-01-14

申请人： Megumi Yokoi ,  Masaki Ukai

发明人： Megumi Yokoi ,  Masaki Ukai

IPC分类号： G06F12/12

CPC分类号： G06F9/3806 ,  G06F12/124 ,  G06F12/125

摘要： A storage device in a set associative system includes N-pieces (N is an integer of 2 or larger) of ways each having a plurality of entries containing at least replace flags and predetermined data, an acquisition unit acquiring the replace flags contained in the entries specified by the same address from the N-pieces of ways, and a selection unit selecting a replace target way on the basis of the replace flags acquired by the acquisition unit.

摘要翻译： 集合关联系统中的存储装置包括各自具有包含至少替换标志和预定数据的多个条目的方式的N个（N是2或更大的整数），获取单元获取包含在条目中的替换标志 由N个方式由相同的地址指定，以及选择单元，基于由获取单元获取的替换标志来选择替换目标方式。

公开(公告)号：US20050278516A1

公开(公告)日：2005-12-15

申请号：US11207825

申请日：2005-08-22

申请人： Masaki Ukai ,  Kyoko Tashima ,  Aiichiro Inoue

发明人： Masaki Ukai ,  Kyoko Tashima ,  Aiichiro Inoue

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3844 ,  G06F9/3861

摘要： An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.

摘要翻译： 信息处理装置能够推测性地执行诸如流水线/超标量/无序执行并且配备有分支预测机制（分支历史）的执行。 信息处理装置为了处理包含子程序的高速指令序列，还配备有返回地址堆栈，在完成子程序调用/返回对应的执行时堆栈操作被激活 指令和条目指定单元（指针），以便调整在完成指令之前执行的指令提取导致的时间差，指向相对于堆栈前端的位置，并且调整在推测上执行的指令提取之间的时间差 在完成执行与子程序调用/返回相对应的分支指令时以及在与指令获取同步地预测子程序调用/返回时，提前执行指令并完成指令。 采用由入口指定单元指向的堆栈位置的入口位置作为子程序调用/返回预测地址，因此子程序返回地址的预测变得更准确，处理速度变高。

公开(公告)号：US20050246506A1

公开(公告)日：2005-11-03

申请号：US10937253

申请日：2004-09-10

申请人： Masaki Ukai

发明人： Masaki Ukai

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F12/00

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/526 ,  G06F2209/521

摘要： In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.

摘要翻译： 一种用于控制通过高速缓冲存储器访问存储设备的信息的处理器的方法，当读取存储在存储设备的目标地址或地址范围中的信息时，监视是否存在对地址或地址范围的更新访问 并且还将处理器输入到暂停状态，该状态使用从作为触发器的另一处理器对存储设备的更新访问的发生而被释放。

公开(公告)号：US20050198480A1

公开(公告)日：2005-09-08

申请号：US11125212

申请日：2005-05-10

申请人： Masaki Ukai ,  Aiichiro Inoue

发明人： Masaki Ukai ,  Aiichiro Inoue

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3802

摘要： An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

摘要翻译： 一种指令控制装置和方法，与包括高速缓冲存储器，下位存储器，向第一转移指令的指令取出请求发出到高速缓冲存储器的指令取出装置的装置一起使用，以及指令控制装置， 存储在高速缓冲存储器中的指令序列。 该装置和方法为第二分支指令的目标预预取目标指令序列。 当第一分支指令的目标的目标指令序列不在高速缓冲存储器中时，基于过去历史的预定指令序列被预先从下部存储器传送到高速缓冲存储器。

公开(公告)号：US06912650B2

公开(公告)日：2005-06-28

申请号：US09793559

申请日：2001-02-27

申请人： Masaki Ukai ,  Aiichiro Inoue

发明人： Masaki Ukai ,  Aiichiro Inoue

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3802

摘要： An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

摘要翻译： 一种指令控制装置和方法，与包括高速缓冲存储器，下位存储器，向第一转移指令的指令取出请求发出到高速缓冲存储器的指令取出装置的装置一起使用，以及指令控制装置， 存储在高速缓冲存储器中的指令序列。 该装置和方法为第二分支指令的目标预预取目标指令序列。 当第一分支指令的目标的目标指令序列不在高速缓冲存储器中时，基于过去历史的预定指令序列被预先从下部存储器传送到高速缓冲存储器。

公开(公告)号：US08312218B2

公开(公告)日：2012-11-13

申请号：US12230244

申请日：2008-08-26

申请人： Masaki Ukai

发明人： Masaki Ukai

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0844 ,  G06F12/0857 ,  G06F12/0859 ,  G06F2212/1016 ,  G06F2212/1056

摘要： A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.

摘要翻译： 一种将数据写入高速缓冲存储器的高速缓存控制器，包括保持经由外部总线流入的数据的第一缓冲单元，检索要写入高速缓冲存储器的一段数据的第二缓冲单元，以及写入控制单元 其控制将由第二缓冲单元检索的数据片段写入缓存存储器。

公开(公告)号：US08301969B2

公开(公告)日：2012-10-30

申请号：US12198577

申请日：2008-08-26

申请人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

发明人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

IPC分类号： H03M13/00

CPC分类号： H04L1/0042 ,  G06F11/349 ,  H04L1/0047 ,  H04L25/4915

摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

摘要翻译： 发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。 发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。 在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定 （33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。