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    Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
    21.
    发明授权
    Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
    使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法

    公开(公告)号：US5372973A

    公开(公告)日：1994-12-13

    申请号：US53794

    申请日：1993-04-27

    Applicant: Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

    Inventor： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

    IPC: H01J1/304 ,  H01J9/02 ,  H01L21/3105 ,  H01L21/465

    CPC classification number: H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

    Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

    Abstract translation: 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

    Method of selectively etching silicon dioxide dielectric layers on semiconductor wafers
    22.
    发明授权
    Method of selectively etching silicon dioxide dielectric layers on semiconductor wafers 失效
    在半导体晶片上选择性地蚀刻二氧化硅电介质层的方法

    公开(公告)号：US5300463A

    公开(公告)日：1994-04-05

    申请号：US847368

    申请日：1992-03-06

    Applicant: David A. Cathey ,  J. Brett Rolfson

    Inventor： David A. Cathey ,  J. Brett Rolfson

    IPC: H01L21/311 ,  H01L21/00 ,  H01L21/02 ,  H01L21/465

    CPC classification number: H01L21/31111

    Abstract: A method of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers comprises: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) providing a layer of doped SiO.sub.2 atop the layer of undoped SiO.sub.2 ; and c) wet etching the layer of doped SiO.sub.2 selectively relative to the undoped layer of SiO.sub.2 utilizing an acid solution, the acid solution comprising a mixture of at least two different mineral acids provided in a selected ratio relative to one another, one of the mineral acids being HF. The preferred volumetric ratio of other mineral acids in the acid solution to HF in the acid solution is from 20:1 to 110:1, with a ratio of from 45:1 to 65:1 being most preferred. Example acids to be combined with the HF include H.sub.2 SO.sub.4, HCl, HNO.sub.3, H.sub.3 PO.sub.4, HBr, HI, HClO.sub.4, and HIO.sub.4, or mixtures thereof.

    Abstract translation: 在半导体晶片的处理中利用和蚀刻SiO 2的方法包括：a）在晶片顶上提供未掺杂的SiO 2层; b）在未掺杂的SiO 2层的顶部提供掺杂SiO 2层; 和c）使用酸溶液相对于未掺杂的SiO 2层选择性地浸蚀掺杂SiO 2层，所述酸溶液包含以相对于彼此的选定比率提供的至少两种不同的无机酸的混合物，所述矿物质之一 酸是HF。 在酸溶液中酸溶液中的其它无机酸与HF的优选体积比为20:1至110:1，最优选的比例为45:1至65:1。 与HF组合的实例酸包括H 2 SO 4，HCl，HNO 3，H 3 PO 4，HBr，HI，HClO 4和HIO 4，或其混合物。

    Method of increasing capacitance by surface roughening in semiconductor wafer processing
    23.
    发明授权
    Method of increasing capacitance by surface roughening in semiconductor wafer processing 失效
    通过半导体晶片加工中的表面粗糙度增加电容的方法

    公开(公告)号：US5244842A

    公开(公告)日：1993-09-14

    申请号：US812061

    申请日：1991-12-17

    Applicant: David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

    Inventor： David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

    IPC: H01L21/02 ,  H01L21/334

    CPC classification number: H01L28/84 ,  H01L29/66181 ,  Y10S438/964

    Abstract: A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer inducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.

    Abstract translation: 通过在半导体晶片处理中通过表面粗糙度增加电容的方法包括以下步骤：a）在基板顶部施加第一层材料，从而限定暴露的表面; b）不连续地将离散的固体颗粒粘附到第一层暴露表面以使暴露的表面粗糙; 以及c）在第一层上方施加第二层材料并粘附固体颗粒以限定外表面，粘附到第一层的颗粒引起粗糙度进入外表面，从而增加其表面积，从而增加其中的第二层的电容 最终的晶圆结构。

    Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
    24.
    发明授权
    Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
    使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法

    公开(公告)号：US5229331A

    公开(公告)日：1993-07-20

    申请号：US837453

    申请日：1992-02-14

    Applicant: Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

    Inventor： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

    IPC: H01J1/304 ,  H01J9/02 ,  H01L21/3105

    CPC classification number: H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

    Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

    Abstract translation: 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

    Emitter
    27.
    发明授权
    Emitter 失效
    发射器

    公开(公告)号：US07064476B2

    公开(公告)日：2006-06-20

    申请号：US09759746

    申请日：2001-01-12

    Applicant: David A. Cathey

    Inventor： David A. Cathey

    IPC: H01J1/14

    CPC classification number: H01J1/3044 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  Y10S148/116 ,  Y10S148/172 ,  Y10S438/978

    Abstract: Electron emitters and a method of fabricating emitters are disclosed, having a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

    Abstract translation: 公开了电子发射器和制造发射体的方法，其具有杂质的浓度梯度，使得最高浓度的杂质位于发射体的顶点并朝向发射体的基底减小。 该方法包括掺杂，图案化，蚀刻和氧化衬底的步骤，从而形成具有杂质梯度的发射体。

    Large-area FED apparatus and method for making same
    29.
    发明授权
    Large-area FED apparatus and method for making same 有权

    公开(公告)号：US06495956B2

    公开(公告)日：2002-12-17

    申请号：US09867912

    申请日：2001-05-30

    Applicant: David A. Cathey ,  Jimmy J. Browning

    Inventor： David A. Cathey ,  Jimmy J. Browning

    IPC: H01J1942

    CPC classification number: H01J31/123 ,  H01J9/025 ,  H01J9/185 ,  H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/863

    Abstract: A large-area field emission device (“FED”) which is sealed under a predetermined level of vacuum pressure and method for making same includes a large-area substrate, an emitter electrode structure disposed on the substrate such that the emitter structure is disposed over a substantial portion of the substrate, a plurality of groups of micropoints, with each group having a predetermined number of micropoints and with each group being disposed at discrete positions on the emitter electrode structure, an insulating layer disposed over the substrate, with the insulating layer having openings therethrough which have a diameter within a predetermined range, and with each openings surrounding at least a portion a micropoint, an extraction structure disposed on the insulating layer, with the extraction structure having openings therethrough which have a diameter within a predetermined range, with each openings surrounding at least a portion of a micropoint, and with the openings in the extraction structure being aligned with openings in the insulating layer, a faceplate disposed above and spaced away from the extraction structure that is transparent to predetermined wavelengths of light, an indium tin oxide (“ITO”) layer disposed on a surface of the faceplate towards the extraction structure, a matrix member disposed on the ITO layer, with the matrix member defining areas of the ITO surface that are to serve as pixel areas, with the pixel areas being aligned with the micropoints of a group micropoints, cathodoluminescent material disposed on the ITO in a plurality pixel areas, with the cathodoluminescent material at a particular pixel area being aligned to receive electron emitted from the micropoints associated that pixel area, and a plurality of spacers disposed between the faceplate and the extraction structure at predetermined locations, with each spacer having a height and cross-sectional shape commensurate with stresses that spacer will encounter caused by the vacuum pressure within the FED.

    Anodically-bonded elements for flat panel displays
    30.
    发明授权
    Anodically-bonded elements for flat panel displays 失效
    用于平板显示器的阳极接合元件

    公开(公告)号：US06422906B1

    公开(公告)日：2002-07-23

    申请号：US09350081

    申请日：1999-07-08

    Applicant: James J. Hofmann ,  Jason B. Elledge ,  Zhong-Yi Xia ,  David A. Cathey

    Inventor： James J. Hofmann ,  Jason B. Elledge ,  Zhong-Yi Xia ,  David A. Cathey

    IPC: H01J924

    CPC classification number: H01J9/242 ,  H01J9/185 ,  H01J2329/8625 ,  H01J2329/863

    Abstract: A process is disclosed for anodically bonding an array of spacer columns to one of the inner major faces on one of the generally planar plates of an evacuated, flat-panel video display. The process includes the steps of: providing a generally planar plate having a plurality of spacer column attachment sites; providing electrical interconnection between all attachment sites; coating each attachment site with a patch of oxidizable material; providing an array of unattached permanent glass spacer columns, each unattached permanent spacer column being of uniform length and being positioned longitudinally perpendicular to a single plane, with the plane intersecting the midpoint of each unattached spacer column; positioning the array such that an end of one permanent spacer column is in contact with the oxidizable material patch at each attachment site; and anodically bonding the contacting end of each permanent spacer column to the oxidizable material layer. The invention also includes an evacuated flat panel display having spacer structures which are anodically bonded to an internal major face of the display, as well as a face plate assembly manufactured by the aforestated process.

    Abstract translation: 公开了一种用于将隔离柱阵列阳极结合到抽空的平板显示器的一个平面板上的内主表面之一的工艺。 该方法包括以下步骤：提供具有多个间隔柱附着位点的大致平面的板; 提供所有附件位置之间的电气互连; 用一块可氧化材料涂覆每个附着部位; 提供一组未连接的永久性玻璃间隔柱，每个未连接的永久间隔柱具有均匀的长度并且纵向垂直于单个平面定位，该平面与每个未连接的间隔柱的中点相交; 定位阵列使得一个永久间隔柱的末端在每个附着位置与可氧化材料贴片接触; 并将每个永久间隔柱的接触端阳极结合到可氧化材料层上。 本发明还包括具有阳极结合到显示器的内部主面的间隔结构的抽真空平板显示器以及通过前述方法制造的面板组件。

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