公开(公告)号：US07812633B1

公开(公告)日：2010-10-12

申请号：US11584308

申请日：2006-10-20

申请人： Andy L. Lee ,  David Lewis ,  Philip Pan ,  James G. Schleicher, II

发明人： Andy L. Lee ,  David Lewis ,  Philip Pan ,  James G. Schleicher, II

IPC分类号： H03K19/173 ,  H01L25/00

CPC分类号： H03K19/17728

摘要： A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

摘要翻译： 具有具有N级查找表（LUT）的逻辑元件，用于执行非LUT逻辑功能的专用硬件的可编程逻辑器件以及被配置为选择性地迫使N级LUT内的多路复用级的过载元件 选择一个或多个LUT配置位输入或非LUT逻辑功能的输出作为LUT的输出。 在各种实施例中，非LUT功能可以包括加法，减法，乘法，除法，数字信号处理，存储器存储等

公开(公告)号：US07740463B2

公开(公告)日：2010-06-22

申请号：US10612072

申请日：2003-07-03

申请人： David Lewis ,  David Ganderton ,  Brian Meakin ,  Paolo Ventura ,  Gaetano Brambilla ,  Raffaella Garzia

发明人： David Lewis ,  David Ganderton ,  Brian Meakin ,  Paolo Ventura ,  Gaetano Brambilla ,  Raffaella Garzia

IPC分类号： A61K9/12 ,  A61K47/00 ,  A61M11/00

CPC分类号： A61K9/008 ,  A61K9/12 ,  A61M15/009 ,  Y10S514/958

摘要： The invention relates to the use of pressurised metered dose inhalers (MDIs) having part or all of their internal surfaces consisting of stainless steel, anodised aluminium or lined with an inert organic coating; and to compositions to be delivered with said MDIs.

摘要翻译： 本发明涉及使用加压计量吸入器（MDI），其具有由不锈钢，阳极氧化铝或惰性有机涂层衬里组成的部分或全部内表面; 以及与所述MDI一起递送的组合物。

公开(公告)号：US07716623B1

公开(公告)日：2010-05-11

申请号：US12580038

申请日：2009-10-15

申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

IPC分类号： H03K17/693

CPC分类号： H03K19/17736

摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LAB）“的群集在一起的逻辑元件（”LE“）。 为了节省面积，与现有技术相比，减少或消除了局部反馈资源（用于将LAB中的LE的输出反馈到LAB中的LE的输入）。 因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须通过LAB的通用输入路由资源路由，所以保存那些 资源。 例如，通过在确定在LAB中一起实现哪些逻辑功能时，更重要的是找到具有共同输入的逻辑功能。

公开(公告)号：US20090315588A1

公开(公告)日：2009-12-24

申请号：US12548976

申请日：2009-08-27

申请人： David Lewis

发明人： David Lewis

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1735

摘要： The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely.

摘要翻译： 结构化专用集成电路（结构化ASIC）的逻辑单元（HLE）可用于提供各种尺寸的存储块。 可以采用几种技术中的一种或多种技术来促进对可能具有针对这种存储块的不同要求（例如，在尺寸方面）的各种用户设计。 例如，可以提供预先设计的存储器块的宏，然后根据需要进行组合以提供各种大小的存储块。 存储器电路的某些部分（例如，存储器核心）可以观察到放置约束，而其他部分（例如，地址预解码器电路，写入和读取数据寄存器等）可以相对自由地定位。

公开(公告)号：US07601336B2

公开(公告)日：2009-10-13

申请号：US10435032

申请日：2003-05-12

申请人： David Lewis ,  Davis Ganderton ,  Brian Meakin ,  Paolo Ventura ,  Gaetano Brambilla ,  Raffaella Garzia

发明人： David Lewis ,  Davis Ganderton ,  Brian Meakin ,  Paolo Ventura ,  Gaetano Brambilla ,  Raffaella Garzia

IPC分类号： A61K9/12 ,  A61K9/14 ,  A61K9/00

CPC分类号： A61K9/008 ,  Y10S514/958

摘要： A composition for use in an aerosol inhaler, the composition comprising an active material, a propellant containing a hydrofluoroalkane (HFA), a cosolvent and further comprising a low volatility component to increase the mass median aerodynamic diameter (MMAD) of the aerosol particles on actuation of the inhaler, filling of an aerosol container and use of the composition for the administration of active materials by inhalation.

摘要翻译： 用于气溶胶吸入器的组合物，所述组合物包含活性物质，含有氢氟烷烃（HFA）的助推剂，共溶剂，并且还包含低挥发性组分以增加气雾剂颗粒在致动时的质量中值空气动力学直径（MMAD） 的吸入器，气雾剂容器的填充以及该组合物用于通过吸入给药活性物质的用途。

公开(公告)号：US20090243687A1

公开(公告)日：2009-10-01

申请号：US12060795

申请日：2008-04-01

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/286 ,  H03K3/00 ,  G06F1/04 ,  H03K3/037

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US07589555B1

公开(公告)日：2009-09-15

申请号：US11651364

申请日：2007-01-08

申请人： David Lewis

发明人： David Lewis

IPC分类号： H03K19/173

CPC分类号： H03K19/1735

摘要： The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely.

摘要翻译： 结构化专用集成电路（结构化ASIC）的逻辑单元（HLE）可用于提供各种尺寸的存储块。 可以采用几种技术中的一种或多种技术来促进对可能具有针对这种存储块的不同要求（例如，在尺寸方面）的各种用户设计。 例如，可以提供预先设计的存储器块的宏，然后根据需要进行组合以提供各种大小的存储块。 存储器电路的某些部分（例如，存储器核心）可以观察到放置约束，而其他部分（例如，地址预解码器电路，写入和读取数据寄存器等）可以相对自由地定位。

公开(公告)号：US20090224800A1

公开(公告)日：2009-09-10

申请号：US12465464

申请日：2009-05-13

申请人： Andy L. Lee ,  Cameron McClintock ,  Brian Johnson ,  Richard Cliff ,  Srinivas Reddy ,  Chris Lane ,  Paul Leventis ,  Vaughn Timothy Betz ,  David Lewis

发明人： Andy L. Lee ,  Cameron McClintock ,  Brian Johnson ,  Richard Cliff ,  Srinivas Reddy ,  Chris Lane ,  Paul Leventis ,  Vaughn Timothy Betz ,  David Lewis

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

摘要翻译： 根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。 提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

公开(公告)号：US07583103B2

公开(公告)日：2009-09-01

申请号：US11731125

申请日：2007-03-30

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/173 ,  H03K19/098 ,  H03L7/00 ,  H03B19/00

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。

公开(公告)号：US07558812B1

公开(公告)日：2009-07-07

申请号：US10723104

申请日：2003-11-26

申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC分类号： G06F7/38

CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。