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33 条记录 (耗时 0.055 秒)

    SYSTEM, METHOD AND STORAGE MEDIUM FOR CONTROLLING ASYNCHRONOUS UPDATES TO A REGISTER
    21.
    发明申请
    SYSTEM, METHOD AND STORAGE MEDIUM FOR CONTROLLING ASYNCHRONOUS UPDATES TO A REGISTER 失效
    用于控制寄存器异步更新的系统，方法和存储介质

    公开(公告)号：US20080189492A1

    公开(公告)日：2008-08-07

    申请号：US12105816

    申请日：2008-04-18

    申请人： Michael Billeci

    发明人： Michael Billeci

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30098 ,  G06F9/52

    摘要： A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

    摘要翻译： 一种用于控制对寄存器的异步更新的系统，该系统包括可由硬件和软件异步地更新的通常可访问的寄存器。 该系统还包括与寄存器通信的保护逻辑。 保护逻辑包括防止硬件对寄存器的更新被软件更新覆盖的电路。

    METHOD AND SYSTEM FOR PERFORMING A HARDWARE TRACE
    22.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING A HARDWARE TRACE 有权
    用于执行硬件跟踪的方法和系统

    公开(公告)号：US20080016409A1

    公开(公告)日：2008-01-17

    申请号：US11779561

    申请日：2007-07-18

    申请人： Michael Billeci ,  Timothy Slegel

    发明人： Michael Billeci ,  Timothy Slegel

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2268

    摘要： Methods and systems for pre-detecting a hardware hang in a processor. The methods comprise maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts of a hang limit; initiating trace capture in response to detecting said pre-hang condition; and detecting a hang condition if said count equals said hang limit.

    摘要翻译： 用于预检测处理器中的硬件挂起的方法和系统。 所述方法包括在预定义的时间间隔内保持多个周期的计数，而不完成指令; 如果所述计数在暂停限制的N个计数内，则检测预挂起状态; 响应于检测到所述预悬挂条件而启动跟踪捕获; 并且如果所述计数等于所述挂起限制，则检测挂起状况。

    Intermediate register mapper
    24.
    发明授权
    Intermediate register mapper 失效
    中间寄存器映射器

    公开(公告)号：US08683180B2

    公开(公告)日：2014-03-25

    申请号：US12578272

    申请日：2009-10-13

    申请人： Brian D. Barrick ,  Michael Billeci ,  Lee E. Eisen

    发明人： Brian D. Barrick ,  Michael Billeci ,  Lee E. Eisen

    IPC分类号： G06F15/00

    CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857

    摘要： A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse.

    摘要翻译： 一种在寄存器重命名机制中采用中间寄存器映射器的方法，处理器和计算机程序产品。 逻辑寄存器查找确定是否发生了与调度指令相关联的逻辑寄存器的命中。 在这方面，逻辑寄存器查找在至少一个寄存器映射器中从一组寄存器映射器搜索，包括架构化寄存器映射器，统一主映射器和中间寄存器映射器。 在一组寄存器映射器中选择对逻辑寄存器的单次命中。 如果在统一主映像器中具有映射器条目的指令已经完成但尚未完成，则统一主映射器中的寄存器映射器条目的映射内容被移动到中间寄存器映射器，并且统一寄存器映射器条目被释放，因此 增加可用于重用的多个统一的主映射器条目。

    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA
    26.
    发明申请
    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA 失效
    收集计算机处理器仪表数据

    公开(公告)号：US20110154298A1

    公开(公告)日：2011-06-23

    申请号：US12645687

    申请日：2009-12-23

    申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    IPC分类号： G06F9/44

    CPC分类号： G06F11/348 ,  G06F11/3409

    摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

    摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

    System and method for the capture and preservation of intermediate error state data
    27.
    发明授权
    System and method for the capture and preservation of intermediate error state data 有权
    捕获和保存中间错误状态数据的系统和方法

    公开(公告)号：US07814374B2

    公开(公告)日：2010-10-12

    申请号：US11625006

    申请日：2007-01-19

    申请人： Douglas Balazich ,  Michael Billeci ,  Anthony Saporito ,  Timothy J. Slegel

    发明人： Douglas Balazich ,  Michael Billeci ,  Anthony Saporito ,  Timothy J. Slegel

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/0778

    摘要： A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.

    摘要翻译： 一种具有捕获和保存中间机器错误状态数据的能力的多处理器芯片系统，其中所述系统包括第二级高速缓存，其中所述第二级高速缓存通常与初级和次级处理核心以及至少两个主要错误事件寄存器 ，其中每个主要错误事件寄存器在逻辑上与相应的处理核心相关联。 此外，至少两个次级错误事件寄存器，其中每个次级错误事件寄存器在逻辑上与相应的处理核心相关联，以及至少两个子主要错误累积寄存器，其中每个子主要错误累积寄存器在逻辑上与相应的 主要错误事件寄存器和辅助错误事件寄存器。

    SYSTEM AND METHOD FOR THE CAPTURE AND PRESERVATION OF INTERMEDIATE ERROR STATE DATA
    28.
    发明申请
    SYSTEM AND METHOD FOR THE CAPTURE AND PRESERVATION OF INTERMEDIATE ERROR STATE DATA 有权
    用于捕获和保留中间错误状态数据的系统和方法

    公开(公告)号：US20080178048A1

    公开(公告)日：2008-07-24

    申请号：US11625006

    申请日：2007-01-19

    申请人： Douglas Balazich ,  Michael Billeci ,  Anthony Saporito ,  Timothy J. Slegel

    发明人： Douglas Balazich ,  Michael Billeci ,  Anthony Saporito ,  Timothy J. Slegel

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/0778

    摘要： A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.

    摘要翻译： 一种具有捕获和保存中间机器错误状态数据的能力的多处理器芯片系统，其中所述系统包括第二级高速缓存，其中所述第二级高速缓存通常与初级和次级处理核心以及至少两个主要错误事件寄存器 ，其中每个主要错误事件寄存器在逻辑上与相应的处理核心相关联。 此外，至少两个次级错误事件寄存器，其中每个次级错误事件寄存器在逻辑上与相应的处理核心相关联，以及至少两个子主要错误累积寄存器，其中每个子主要错误累积寄存器在逻辑上与相应的 主要错误事件寄存器和辅助错误事件寄存器。

    System, method and storage medium for controlling asynchronous updates to a register
    30.
    发明授权
    System, method and storage medium for controlling asynchronous updates to a register 失效
    用于控制对寄存器的异步更新的系统，方法和存储介质

    公开(公告)号：US07380077B2

    公开(公告)日：2008-05-27

    申请号：US11625408

    申请日：2007-01-22

    申请人： Michael Billeci

    发明人： Michael Billeci

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30098 ,  G06F9/52

    摘要： A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

    摘要翻译： 一种用于控制对寄存器的异步更新的系统，该系统包括可由硬件和软件异步地更新的通常可访问的寄存器。 该系统还包括与寄存器通信的保护逻辑。 保护逻辑包括防止硬件对寄存器的更新被软件更新覆盖的电路。